An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques

ABSTRACT

We evaluate the effectiveness of dual-V_t design in the presence of both subthreshold leakage and leakage due to gate oxide tunneling. At the device level, we use detailed HSPICE simulation to investigate the total leakage impact of three methods of dual-V_t implementation: multiple channel doping, channel length, and oxide thickness. At the system level, we generate and characterize a standard cell library and apply three representative delay-constrained leakage minimization dual-V_t assignment algorithms to the ISCAS'85 combinational benchmark circuits. Results show that oxide thickness modulation effectively reduces total leakage power consumption, but channel doping and channel length modulation are less effective.

REFERENCES

• 1: M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits: Managing Leakage Power Kluwer Publishers, 2003.
• 2: Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]
• 3: Q. Wang and S. B. K. Vrudhula, "Algorithms for minimizing standby power in deep submicrometer, dual-vt cmos circuits," TCAD vol. 21, no. 3, pp. 306--318, March 2002.
• 4: Ankur Srivastava, Simultaneous Vt selection and assignment for leakage optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871543]
• 5: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.227, September 17-20, 2000
• 6: Anup Kumar Sultania , Dennis Sylvester , Sachin S. Sapatnekar, Tradeoffs between date oxide leakage and delay for dual T_ox circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996773]
• 7: Pankaj Pant , Rabindra K. Roy , Abhijit Chatterjee, Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.2, p.390-394, April 2001 [doi>10.1109/92.924061]
• 8: Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514042]
• 9: Feng Gao , John P. Hayes, Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.258-264, October 11-13, 2004
• 10: Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.316, September 16-18, 2002
• 11: Ashish Srivastava , Dennis Sylvester , David Blaauw, Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996777]
• 12: W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013276]
• 13: Dongwoo Lee , David Blaauw, Static leakage reduction through simultaneous threshold voltage and state assignment, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775881]
• 14: Dongwoo Lee , Harmander Deogun , David Blaauw , Dennis Sylvester, Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization, Proceedings of the conference on Design, automation and test in Europe, p.10494, February 16-20, 2004
• 15: "ITRS" http://public. itrs. net, 2003.
• 16: Amit Agarwal , Kunhyuk Kang , Swarup K. Bhunia , James D. Gallagher , Kaushik Roy, Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA [doi>10.1145/1077603.1077609]
• 17: Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive mosfet and inter-connect modeling for early circuit design," in CICC 2000, pp. 201--204.
• 18: http://www-device. eecs. berkeley. edu/~ptm.
• 19: Yuan Taur , Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, New York, NY, 1998

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration); Advanced technologies

General Terms:
Algorithms, Design, Performance

Keywords:
dual threshold voltage, gate oxide tunneling, low power circuit design, subthreshold leakage