Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning

Full text

Pdf (286 KB)

Source

Great Lakes Symposium on VLSI archive
Proceedings of the 16th ACM Great Lakes symposium on VLSI table of contents

Philadelphia, PA, USA

POSTER SESSION: Poster session 1 table of contents

Pages: 91 - 94

Year of Publication: 2006

ISBN:1-59593-347-6

Authors

Xiangyuan Liu	National University of Defense Technology, Hunan, P. R. China
Shuming Chen	National University of Defense Technology, Hunan, P. R. China

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 37, Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1127908.1127932 What is a DOI?

ABSTRACT

In this paper, we present a lookup table based model for delay and power estimation of low-swing interconnects: LSIEM. It can be used during high-level design planning, synthesis, and simulation of interconnect-centric VDSM designs. LSIEM is an accurate and efficient high-level estimation model. It has been tested on a wide range of parameters and shown to have over 90% accuracy with respect to HSPICE simulation results.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Banerjee, K., and Mehrotra, A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. on Electron Devices, 49, 11 (2002), 2001--2007.
	2	Kay, R., and Pileggi, L. T. EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. on CAD, 17, 1 (1998), 40--49.
	3	Dally, W. A single-chip terabit switch. In Proc. of Hot Chips 13. (Palo Alto, USA, 2001). 19--21.
	4	Liu, X. Y., and Chen, S. M. Interconnect Delay Optimization Using a Novel Hybrid Insertion Strategy. In Proc. of ASICON'05. (Shanghai, China, 2005). 772--775.
	5	Cong, J., and Pan, Z. D. Interconnect performance estimation models for design planning. IEEE Trans. on CAD of ICs and Systems, 20, 6 (2001), 739--752.
	6	Pallav Gupta , Lin Zhong , Niraj K. Jha, A High-level Interconnect Power Model for Design Space Exploration, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.551, November 09-13, 2003 [doi>10.1109/ICCAD.2003.10]
	7	Davide Bertozzi , Luca Benini , Bruno Ricco', Parametric timing and power macromodels for high level simulation of low-swing interconnects, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566488]