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Shuttle mask floorplanning with modified alpha-restricted grid
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 16th ACM Great Lakes symposium on VLSI table of contents
Philadelphia, PA, USA
SESSION: Partitioning and floorplanning table of contents
Pages: 85 - 90  
Year of Publication: 2006
ISBN:1-59593-347-6
Authors
Royce L.S. Ching  The Chinese University of Hong Kong
Evangeline F.Y. Young  The Chinese University of Hong Kong
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Multi Project Wafer (MPW) is an efficient method to share the mask cost among projects of different enterprisers for prototyping and low-volume manufacturing of IC designs. Designs from multiple customers can be put on one single mask substrate to produce MPW. Unlike traditional floorplanning, we need to consider the side-to-side wafer dicing constraint of the diamond sawing technology and different technology processes used in different projects for this problem. In our work, we use a branch and bound algorithm to solve this problem with a grid packing approach. We defined a special type of grid, called the modified α-restricted grid, to reduce the size of the searching solution space. Unlike many previous works, we consider non-zero margin width (but copies of the same design will have the same margin width), different technology processes of the projects, multiple copies of the same design on a mask, etc. In each searching step, our algorithm generates a grid and try to pack the dies into the grid by a Two Phase Packing(TPP) heuristic. We consider circular wafers and the objective is to minimize the total production cost. The experimental results are very promising and our approach can out-perform the most up-to-date works on this problem.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Andersson, J. Gudmundsson, and C. Levcopoulos. Chips on wafers. In Proceedings of Workshop on Algorithms and Data Structures, 2003.
 
2
G. Xu, R. Tian, D.F. Wong, and A. Reich. Shuttle mask floorplanning. In Proceedings of SPIE, volume 5256, pages 185--194, 2003.
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4
G. Xu, R. Tian, Z. Pan, and D.F. Wong. A multi-objective floorplanner for shuttle mask optimization. In Proceedings of SPIE, volume 5567, 2004.
 
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A.B. Kahng, I. Mandoiu, X. Xu, and A. Zelikovsky. Yield-driven multi-project reticle design and wafer dicing. In 25th BACUS Symposium on Photomask Technology and Management, October 2005.
 
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Meng-Chiou Wu and Rung-Bin Lin. Reticle floorplanning of flexible chips for multi-project wafers. In ASPDAC, 2006.


Collaborative Colleagues:
Royce L.S. Ching: colleagues
Evangeline F.Y. Young: colleagues