| HW/SW partitioning techniques for multi-mode multi-task embedded applications |
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Great Lakes Symposium on VLSI
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Proceedings of the 16th ACM Great Lakes symposium on VLSI
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Philadelphia, PA, USA
SESSION: CAD for embedded systems
table of contents
Pages: 25 - 30
Year of Publication: 2006
ISBN:1-59593-347-6
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Downloads (6 Weeks): 6, Downloads (12 Months): 33, Citation Count: 0
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ABSTRACT
An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this paper, we address an important HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources,(2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications, which aims to solve the subproblems 1, 2 and 3 effectively in an integrated fashion. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications (i.e., to find a globally optimized allocation/mapping of processing resources with feasible execution schedule of modules).
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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N. Audsley, A. Burns, M. Richardsons, and W. Wellings, "Hard Real-time Scheduling: The Deadline-monotonic Approach," Proc. IEEE Workshop on Real-time Operating Systems and Software, 1991.
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3
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4
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F. Vahid and T. D. Le, "Extending the Kernighan-Lin Heuristic for Hardware and Software Functional Partitioning," Journal of Design Automation for Embedded Systems, Vol. 2 1997.
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5
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6
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R. P. Dick and N. K. Jha, "MOGAC: A Multiobjective Genetic Algorithm for Hardware-Software Cosynthesis of Distributed Embedded Systems," IEEE TCAD, Vol. 17, No. 10, Oct. 1998.
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7
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Youngsoo Shin , Daehong Kim , Kiyoung Choi, Schedulability-driven performance analysis of multiple mode embedded real-time systems, Proceedings of the 37th conference on Design automation, p.495-500, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337556]
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M. T. Schmitz, B. M. Al-Hashimi and P. Eles, "Cosynthesis of Energy-Efficient Multimode Embedded Systems With Consideration of Mode-Execution Probabilities," IEEE TCAD, vol. 24, no. 2, Feb. 2005.
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A. Kalavade and P.A. Subrahmanyam, "Hardware/Software Partitioning for Multifunction Systems," IEEE TCAD, vol. 9, no.9, Sep. 1998.
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B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Tech. Journal, 1970.
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