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ABSTRACT
Process technology advancements continue to provide designers with more transistors to utilize. In the past, this took the form of designers seeking novel techniques to support the exponential growth of clock frequency scaling. Today, clock frequency scaling has tapered and yet design is still expected to extract value from these additional transistors in the form of better performance and more functionality while staying within a required power envelope. This talk will discuss these trends including the move towards multi-core designs. This talk will also discuss deficiencies in our current design and test methodologies needed to support this and will conclude with challenges that face industry which could be addressed by university research. INDEX TERMS
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