Low cost trace-driven memory simulation using SimPoint

ABSTRACT

Trace-driven memory simulation tools such as MetaSim Tracer [1] capture the address stream of an application during an instrumented program run. Various statistics can be measured using the in-flight address stream including anticipated cache hit rates. This paper reports on performance improvements of MetaSim Tracer gained by using techniques developed in SimPoint [2]. Concurrent research [3] addresses techniques that can be used to reduce the instrumentation overhead involved in memory tracing, and this work addresses a technique that can be used to decrease the amount of cache simulation that is required on top of this. The result is a tool for trace driven cache simulation that is practical to use for memory performance studies of full sized scientific applications.

REFERENCES

• 1: A. Snavely , N. Wolter , L. Carrington, Modeling application performance by convolving machine signatures with application profiles, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, p.149-156, December 02-02, 2001 [doi>10.1109/WWC.2001.16]
• 2: Timothy Sherwood , Erez Perelman , Greg Hamerly , Brad Calder, Automatically characterizing large scale program behavior, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 3: Gao, X., Simon, B. and Snavely, A. ALITER: An Asynchronous Lightweight Instrumentation Tool for Event Recording. Workshop on Binary Instrumentation and Applications, September 2005.
• 4: Carrington, L., Snavely, A., Gao, X. and Wolter, N. A Performance Prediction Framework for Scientific Applications. Workshop on Performance Modeling, June 2003.
• 5: Srivastava, A. and Eustace, A. ATOM: A Flexible Interface for Building High Performance Program Analysis Tools. USENIX Winter Conference, January 1995.
• 6: Gao, X. and Snavely, A. Exploiting Stability to Reduce Time-Space Cost for Memory Tracing. Workshop on Performance Modeling - ICCS, June 2003.
• 7: Lemieux User Information Page. http://www.psc.edu/machines/tcs/lemieux.html, July 2004.
• 8: Bailey, D. The NAS Parallel Benchmarks. Intl. Journal of Supercomputer Applications, vol. 5, no. 3, Fall 1991.
• 9: Allan Snavely , Laura Carrington , Nicole Wolter , Jesus Labarta , Rosa Badia , Avi Purkayastha, A framework for performance modeling and prediction, Proceedings of the 2002 ACM/IEEE conference on Supercomputing, p.1-17, November 16, 2002, Baltimore, Maryland
• 10: Ramamurti, R. and Lohner, R. A Parallel Implicit Incompressible Flow Solver Using Unstructured Meshes. Computers and Fluids, Vol. 25, No. 2, pp. 119--132, 1996.
• 11: Pin User Manual. http://rogue.colorado.edu/Pin/, November 2003.
• 12: Bryan Buck , Jeffrey K. Hollingsworth, An API for Runtime Code Patching, International Journal of High Performance Computing Applications, v.14 n.4, p.317-329, November 2000 [doi>10.1177/109434200001400404]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.5 Testing and Debugging
          Subjects: Tracing
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors

General Terms:
Design, Performance