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Dynamic memory optimization using pool allocation and prefetching
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Volume 33 ,  Issue 5  (December 2005) table of contents
Special issue on the 2005 workshop on binary instrumentation and application
SPECIAL ISSUE: WBIA'05 table of contents
Pages: 27 - 32  
Year of Publication: 2005
ISSN:0163-5964
Authors
Qin Zhao  National University of Singapore, Singapore-MIT Alliance
Rodric Rabbah  MIT Computer Science and Artificial Intelligence Laboratory
Weng-Fai Wong  National University of Singapore, Singapore-MIT Alliance
Publisher
ACM  New York, NY, USA
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ABSTRACT

Heap memory allocation plays an important role in modern applications. Conventional heap allocators, however, generally ignore the underlying memory hierarchy of the system, favoring instead a low runtime overhead and fast response times. Unfortunately, with little concern for the memory hierarchy, the data layout may exhibit poor spatial locality, and degrade cache performance. In this paper, we describe a dynamic heap allocation scheme called pool allocation. The strategy aims to improve cache performance by inspecting memory allocation requests, and allocating memory from appropriate heap pools as dictated by the requesting context. The advantages are two fold. First, by pooling together data with a common context, we expect to improve spatial locality, as data fetched to the caches will contain fewer items from different contexts. If the allocation patterns are closely matched to the traversal patterns, the end result is faster memory performance. Second, by pooling heap objects, we expect access patterns to exhibit more regularity, thus creating more opportunities for data prefetching. Our dynamic memory optimizer exploits the increased regularity to insert prefetch instructions at runtime. The optimizations are implemented in DynamoRIO, a dynamic optimization framework. We evaluate the work using various bench-marks, and measure a 17% speedup over gcc −03 on an Athlon MP, and a 13% speedup on a Pentium 4.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. G. Abraham and B. R. Rau. Predicting load latencies using cache profiling. Technical Report HPL-94-110, Hewlett Packard Labs, Dec 1994.
 
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M. Charney and A. Reeves. Generalized correlation-based hardware prefetching. Technical Report EE-CEG-95-1, Cornell University, Feb. 1995.
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Collaborative Colleagues:
Qin Zhao: colleagues
Rodric Rabbah: colleagues
Weng-Fai Wong: colleagues