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Architectural implications of quantum computing technologies
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Volume 2 ,  Issue 1  (January 2006) table of contents
Pages: 31 - 63  
Year of Publication: 2006
ISSN:1550-4832
Authors
Rodney Van Meter  Keio University and CREST-JST, Kanagawa, Japan
Mark Oskin  University of Washington
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this article we present a classification scheme for quantum computing technologies that is based on the characteristics most relevant to computer systems architecture. The engineering trade-offs of execution speed, decoherence of the quantum states, and size of systems are described. Concurrency, storage capacity, and interconnection network topology influence algorithmic efficiency, while quantum error correction and necessary quantum state measurement are the ultimate drivers of logical clock speed. We discuss several proposed technologies. Finally, we use our taxonomy to explore architectural implications for common arithmetic circuits, examine the implementation of quantum error correction, and discuss cluster-state quantum computation.


REFERENCES

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CITED BY  7

Collaborative Colleagues:
Rodney Van Meter: colleagues
Mark Oskin: colleagues