Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

ABSTRACT

The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly complex task due to its enormous solution space. This paper presents the first algorithm that performs retiming and simultaneous supply/threshold voltage scaling. In our three-step approach, low power retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage scaling makes the best possible supply/threshold voltage assignment under the given clock period constraint set by the retiming. Finally, a post-process further refines the voltage scaling solution by exploiting the remaining timing slack in the circuit. Related experiments show that our min-FF retiming plus simultaneous Vdd/Vth scaling approach reduces the total power consumption by 34% on average compared to the existing max-FF retiming plus Vdd Scaling approach.

REFERENCES

• 1: S. Augsburger and B. Nikolic. Reducing Power with Dual Supply, Dual Threshold and Transistor Sizing. In Proc. IEEE Int. Conf. on Computer Design, 2002.
• 2: Robert W. Brodersen , Mark A. Horowitz , Dejan Markovic , Borivoje Nikolic , Vladimir Stojanovic, Methods for true power minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.35-42, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774578]
• 3: Noureddine Chabini , Ismaïl Chabini , El Mostapha Aboulhamid , Yvon Savaria, Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA [doi>10.1145/764808.764865]
• 4: Noureddine Chabini , Wayne Wolf, Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.573-589, June 2004 [doi>10.1109/TVLSI.2004.827569]
• 5: Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997 [doi>10.1109/92.645070]
• 6: Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001 [doi>10.1109/92.953496]
• 7: Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001 [doi>10.1109/92.953496]
• 8: Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Hsien-Hsin Sean Lee, Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.693, November 09-13, 2003 [doi>10.1109/ICCAD.2003.27]
• 9: GLPK. GLPK (GNU linear programming) kit.
• 10: M. Hamada and Y. Ootaguro. Utilizing Surplus Timing for Power Reduction. In Proc. IEEE Custom Integrated Circuits Conf., 2001.
• 11: W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013276]
• 12: Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871547]
• 13: Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514042]
• 14: S. Kulkarni and D. Sylvester. New level converters and level converting logic circuits for multi-VDD low power design. In Proc. IEEE Int. SOC Conf., 2003.
• 15: M. Papaefthymiou , K. Lalgudi, Fixed-phase retiming for low power design, Proceedings of the 1996 international symposium on Low power electronics and design, p.259-264, August 12-14, 1996, Monterey, California, United States
• 16: C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, pages 5--35, 1991.
• 17: José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
• 18: David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery , Brandon Thompson , Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871545]
• 19: Koichi Nose , Takayasu Sakurai, Optimization of VDD and VTH for low-power and high speed applications, Proceedings of the 2000 conference on Asia South Pacific design automation, p.469-474, January 2000, Yokohama, Japan [doi>10.1145/368434.368755]
• 20: Pankaj Pant , Rabindra K. Roy , Abhijit Chatterjee, Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.2, p.390-394, April 2001 [doi>10.1109/92.924061]
• 21: K. Roy, L. Wei, and Z. Chen. Multiple-Vdd & multiple-Vth CMOS (MVCMOS) for low power applications. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 366--370, 1999.
• 22: Farhana Sheikh , Andreas Kuehlmann , Kurt Keutzer, Minimum-power retiming for dual-supply CMOS circuits, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA [doi>10.1145/589411.589422]
• 23: Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309975]
• 24: A. Srivastava and D. Sylvester. Minimizing Total Power by Simultaneous Vdd/Vth Assignment. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2004.
• 25: Ashish Srivastava , Dennis Sylvester , David Blaauw, Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996777]
• 26: Anup Kumar Sultania , Dennis Sylvester , Sachin S. Sapatnekar, Tradeoffs between date oxide leakage and delay for dual T_ox circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996773]
• 27: Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]
• 28: Q. Wang and S. Vrudhula. Algorithms for minimizing standby power in deep submicron, dual-Vt CMOS circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
low power design, retiming, supply and threshold voltage scaling