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Hybrid transactional memory
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Source Principles and Practice of Parallel Programming archive
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming table of contents
New York, New York, USA
SESSION: Transactional memory table of contents
Pages: 209 - 220  
Year of Publication: 2006
ISBN:1-59593-189-9
Authors
Sanjeev Kumar  Intel Labs, Santa Clara, CA
Michael Chu  University of Michigan, Ann Arbor
Christopher J. Hughes  Intel Labs, Santa Clara, CA
Partha Kundu  Intel Labs, Santa Clara, CA
Anthony Nguyen  Intel Labs, Santa Clara, CA
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 19,   Downloads (12 Months): 154,   Citation Count: 31
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ABSTRACT

High performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they have a number of disadvantages, including possibly unnecessary serialization, and possible deadlock. Transactional memory is an alternative mechanism that makes parallel programming easier. With transactional memory, a transaction provides atomic and serializable operations on an arbitrary set of memory locations. When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.Transactional memory can be implemented in either hardware or software. A straightforward hardware approach can have high performance, but imposes strict limits on the amount of data updated in each transaction. A software approach removes these limits, but incurs high overhead. We propose a novel hybrid hardware-software transactional memory scheme that approaches the performance of a hardware scheme when resources are not exhausted and gracefully falls back to a software scheme otherwise.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. Herlihy. Transactional memory. PLDI' 05 Keynote Address, 2005.
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K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Logtm: Log-based transactional memory. In Proceedings of the 12th Annual International Symposium on High Performance Computer Architecture, 2006.
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R. Rajwar and M. Hill. http://www.cs.wisc.edu/trans-memory/biblio/. Transactional Memory Bibliography, 2005.
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CITED BY  31

Collaborative Colleagues:
Sanjeev Kumar: colleagues
Michael Chu: colleagues
Christopher J. Hughes: colleagues
Partha Kundu: colleagues
Anthony Nguyen: colleagues