| Hybrid transactional memory |
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Principles and Practice of Parallel Programming
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Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
table of contents
New York, New York, USA
SESSION: Transactional memory
table of contents
Pages: 209 - 220
Year of Publication: 2006
ISBN:1-59593-189-9
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Downloads (6 Weeks): 11, Downloads (12 Months): 160, Citation Count: 31
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ABSTRACT
High performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they have a number of disadvantages, including possibly unnecessary serialization, and possible deadlock. Transactional memory is an alternative mechanism that makes parallel programming easier. With transactional memory, a transaction provides atomic and serializable operations on an arbitrary set of memory locations. When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.Transactional memory can be implemented in either hardware or software. A straightforward hardware approach can have high performance, but imposes strict limits on the amount of data updated in each transaction. A software approach removes these limits, but incurs high overhead. We propose a novel hybrid hardware-software transactional memory scheme that approaches the performance of a hardware scheme when resources are not exhausted and gracefully falls back to a software scheme otherwise.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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María Jesús Garzarán , Milos Prvulovic , José María Llabería , Víctor Viñals , Lawrence Rauchwerger , Josep Torrellas, Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.191, February 08-12, 2003
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Lance Hammond , Vicky Wong , Mike Chen , Brian D. Carlstrom , John D. Davis , Ben Hertzberg , Manohar K. Prabhu , Honggo Wijaya , Christos Kozyrakis , Kunle Olukotun, Transactional Memory Coherence and Consistency, Proceedings of the 31st annual international symposium on Computer architecture, p.102, June 19-23, 2004, München, Germany
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Tim Harris , Keir Fraser, Language support for lightweight transactions, Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications, October 26-30, 2003, Anaheim, California, USA
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Tim Harris , Simon Marlow , Simon Peyton-Jones , Maurice Herlihy, Composable memory transactions, Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 15-17, 2005, Chicago, IL, USA
[doi> 10.1145/1065944.1065952]
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M. Herlihy. Transactional memory. PLDI' 05 Keynote Address, 2005.
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Maurice Herlihy , Victor Luchangco , Mark Moir , William N. Scherer, III, Software transactional memory for dynamic-sized data structures, Proceedings of the twenty-second annual symposium on Principles of distributed computing, p.92-101, July 13-16, 2003, Boston, Massachusetts
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K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. Logtm: Log-based transactional memory. In Proceedings of the 12th Annual International Symposium on High Performance Computer Architecture, 2006.
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Milos Prvulovic , María Jesús Garzarán , Lawrence Rauchwerger , Josep Torrellas, Removing architectural bottlenecks to the scalability of speculative parallelization, Proceedings of the 28th annual international symposium on Computer architecture, p.204-215, June 30-July 04, 2001, Göteborg, Sweden
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R. Rajwar and M. Hill. http://www.cs.wisc.edu/trans-memory/biblio/. Transactional Memory Bibliography, 2005.
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J. Greggory Steffan , Christopher B. Colohan , Antonia Zhai , Todd C. Mowry, A scalable approach to thread-level speculation, Proceedings of the 27th annual international symposium on Computer architecture, p.1-12, June 2000, Vancouver, British Columbia, Canada
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CITED BY 31
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JaeWoong Chung , Chi Cao Minh , Austen McDonald , Travis Skare , Hassan Chafi , Brian D. Carlstrom , Christos Kozyrakis , Kunle Olukotun, Tradeoffs in transactional memory virtualization, ACM SIGPLAN Notices, v.41 n.11, November 2006
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Tatiana Shpeisman , Vijay Menon , Ali-Reza Adl-Tabatabai , Steven Balensiefer , Dan Grossman , Richard L. Hudson , Katherine F. Moore , Bratin Saha, Enforcing isolation and ordering in STM, ACM SIGPLAN Notices, v.42 n.6, June 2007
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Miloš Milovanović , Roger Ferrer , Vladimir Gajinov , Osman S. Unsal , Adrian Cristal , Eduard Ayguadé , Mateo Valero, Multithreaded software transactional memory and OpenMP, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.81-88, September 16-16, 2007, Brasov, Romania
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Chi Cao Minh , Martin Trautmann , JaeWoong Chung , Austen McDonald , Nathan Bronson , Jared Casper , Christos Kozyrakis , Kunle Olukotun, An effective hybrid transactional memory system with strong isolation guarantees, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
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Miloš Milovanović , Roger Ferrer , Vladimir Gajinov , Osman S. Unsal , Adrian Cristal , Eduard Ayguadé , Mateo Valero, Nebelung: execution environment for transactional OpenMP, International Journal of Parallel Programming, v.36 n.3, p.326-346, June 2008
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Marc Lupon , Grigorios Magklis , Antonio González, Version management alternatives for hardware transactional memory, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.69-76, October 26-26, 2008, Toronto, Canada
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