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McRT-STM: a high performance software transactional memory system for a multi-core runtime
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Source Principles and Practice of Parallel Programming archive
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming table of contents
New York, New York, USA
SESSION: Transactional memory table of contents
Pages: 187 - 197  
Year of Publication: 2006
ISBN:1-59593-189-9
Authors
Bratin Saha  Intel Corporation
Ali-Reza Adl-Tabatabai  Intel Corporation
Richard L. Hudson  Intel Corporation
Chi Cao Minh  Stanford University, Palo Alto, California
Benjamin Hertzberg  Stanford University, Palo Alto, California
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming.We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs.We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload -- the Linux sendmail application.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Adl-Tabatabai, A., Lewis, B.T., Menon, V.S., Murphy, B.R., Saha, B., and Shpeisman, T. Compiler and runtime optimizations for efficient software transactional memory. To appear PLDI 2006.
 
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CITED BY  56

Collaborative Colleagues:
Bratin Saha: colleagues
Ali-Reza Adl-Tabatabai: colleagues
Richard L. Hudson: colleagues
Chi Cao Minh: colleagues
Benjamin Hertzberg: colleagues