Constructing multiprocessor workload characterizations

ABSTRACT

We present a method for developing a multiple processor workload characterization based on actual system level traces of user and kernel accesses. We trace a single processor system executing an N-processor workload. We then perform static analysis on the trace and produce individual process characterizations. These characterizations can be used to build input workloads for models of multiple processor systems. This provides a method for using real workload traces to drive multiple processor simulations without requiring that a similarly configured machine exist. Additionally, a wealth of static information can be obtained from the traces. As an example, we have traced and analyzed the popular commercial benchmark, TPC-B. We present results from the analysis.

REFERENCES

• 1: A. Agarwal , R. L. Sites , M. Horowitz, ATUM: a new technique for capturing address traces using microcode, Proceedings of the 13th annual international symposium on Computer architecture, p.119-127, June 02-05, 1986, Tokyo, Japan
• 2: R.A. Alfieri. An efficient kernel-based implementation of POSIX threads. In Proceedings of the Summer USENIX Conference, June 1994.
• 3: Anita Borg , R. E. Kessler , David W. Wall, Generation and analysis of very long address traces, Proceedings of the 17th annual international symposium on Computer Architecture, p.270-279, May 28-31, 1990, Seattle, Washington, United States
• 4: B. Chen. Software methods for system address tracing. In The 4th Workshop on Workstation Operating Systems, Napa, California, 1993.
• 5: S. J. Eggers , David R. Keppel , Eric J. Koldinger , Henry M. Levy, Techniques for efficient inline tracing on a shared-memory multiprocessor, Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.37-47, April 1990, Univ. of Colorado, Boulder, Colorado, United States
• 6: Jim Gray, Benchmark Handbook: For Database and Transaction Processing Systems, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1992
• 7: M. A. Holliday. Techniques for cache and memory simulation using address reference traces. International Journal in Computer Simulation, 1:129--151, 1991.
• 8: M. H. Kelley. Multiprocessor aspects of the DG/UX kernel. In Proceedings of the Winter USENIX Conference, pages 85--99, January 1989.
• 9: M. H. Kelley and A. R. Huber. Engineering a (multiprocessor) Unix kernel. In Proceedings of the Autumn European Unix User's Group Conference, pages 7--19, Vienna, Austria, September 1989.
• 10: Motorola Corporation. MC88110 Users Manual, 1991.
• 11: Motorola Corporation. MC88410 Users Manual, 1991.
• 12: D. Nagle, R. Uhlig, and T. Mudge. Monster: A tool for analyzing the interaction between operating systems and computer architectures. Technical report, University of Michigan, May 1992.
• 13: Ali Poursepanj, The PowerPC performance modeling methodology, Communications of the ACM, v.37 n.6, p.47-55, June 1994 [doi>10.1145/175208.175214]
• 14: Colleen D. Schieber , Eric E. Johnson, RATCHET: real-time address trace compression hardware for extended traces, ACM SIGMETRICS Performance Evaluation Review, v.21 n.3-4, p.22-32, April 1994 [doi>10.1145/181840.181842]
• 15: Transaction Processing Performance Council (TPC). TPC Benchmark A, 1989.