Using GALS architecture to reduce the impact of long wire delay on FPGA performance

ABSTRACT

Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. Globally Asynchronous Locally Synchronous (GALS) design is considered a potential solution to this issue. An important design decision in building a GALS FPGA architecture is to determine the appropriate GALS island size. A large GALS island will reduce the asynchronous communication overhead but the interconnect delay inside an island is increased. On the other hand, asynchronous communication overhead could be a major concern for a small GALS island size. In this paper, we propose a design flow to investigate this tradeoff. The input circuit is first divided into partitions according to the specified GALS island size and each partition is then implemented with commercially available CAD tools. The overall system performance is estimated by a performance evaluator. Experimental results validate our design flow and show a performance improvement of around 20% by adopting a GALS architecture.

REFERENCES

• 1: Jason H. Anderson , Farid N. Najm, Switching activity analysis and pre-layout activity prediction for FPGAs, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA [doi>10.1145/639929.639934]
• 2: Xilinx Incorporation. "Virtex-II Platform FPGAs: Complete Data Sheet," June. 04, 2004.
• 3: Jason Cong , Yiping Fan , Xun Yang , Zhiru Zhang, Architecture and synthesis for multi-cycle communication, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640040]
• 4: William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296442]
• 5: Akshay Sharma , Katherine Compton , Carl Ebeling , Scott Hauck, Exploration of pipelined FPGA interconnect structures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968284]
• 6: Scott Hauck , Steven Burns , Gaetano Borriello , Carl Ebeling, An FPGA for Implementing Asynchronous Circuits, IEEE Design & Test, v.11 n.3, p.60-69, July 1994 [doi>10.1109/MDT.1994.303848]
• 7: Rob Payne, Self-Timed FPGA Systems, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.21-35, September 01, 1995
• 8: Ryusuke Konishi , Hideyuki Ito , Hiroshi Nakada , Akira Nagoya , Norbert Imlig , Tsunemichi Shiozawa , Minoru Inamori , Kouichi Nagami , Kiyoshi Oguri, PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI, Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems, p.54, March 11-14, 2001
• 9: John Teifel , Rajit Manohar, Highly pipelined asynchronous FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968300]
• 10: Andrew Royal, Peter Cheung, "Globally Asynchronous Locally Synchronous FPGA Architectures," In Proceedings of 13th International Workshop on Field Programmable Logic and Applications, 2003.
• 11: Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri, "A Dynamic Reconfigurable Asynchronous FPGA Architecture" 14th International Workshop on Field Programmable Logic and Applications, 2004 (to be appeared).
• 12: Adhir Upadhyay , Syed Rafay Hasan , Mohamed Nekili, Optimal partitioning of globally asychronous locally synchronous processor arrays, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA [doi>10.1145/988952.988955]
• 13: Synopsys Inc. "Design Compiler User Guide," June 2003.
• 14: Xilinx Inc., "Xilinx/Synopsys Interface Guide," 2002.
• 15: Xilinx Inc., "Development System Reference Guide -- ISE 5," 2002.
• 16: J Jeon, et al, http://poppy.snu.ac.kr/CDFG/cdfg.html.
• 17: J Miller, H Kramer, "Analysis of Multi-Process Specifications with a Petri-Net Model," In Proceedings of European Design Automation Conference with EURO- VHDL'93, 1993.
• 18: Sujit Dey , Surendra Bommu, Performance analysis of a system of communicating processes, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.590-597, November 09-13, 1997, San Jose, California, United States