| A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264 |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Shanghai, China
Pages: 631 - 634
Year of Publication: 2005
ISBN:0-7803-8737-6
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Authors
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Minho Kim
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Seoul National University, Seoul, Korea
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Ingu Hwang
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Seoul National University, Seoul, Korea
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Soo-Ik Chae
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Seoul National University, Seoul, Korea
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Downloads (6 Weeks): 9, Downloads (12 Months): 98, Citation Count: 11
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 ABSTRACT
We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16x16 PE array, an adder tree and comparators to find all 41 motion vectors and their minimum SADs for the blocks of 16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4. It employs a 2-D datapath and its control of the search area data is simple and regular. The proposed VBSME can achieve 100% PE utilization by employing a preload register and a search data buffer inside each PE and allow real-time processing of 4CIF(704x576) video with 15 fps at 100 Mhz for a search range of [-32~+31].
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Swee Yeow Yap, John V. McCanny, "A VLSI architecture for advanced video coding motion estimation," Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), June 24--26, 2003.
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Cao Wei, Mao Zhi Gang, "A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA," Proc. 5th international conference on ASIC, Oct 21--24, 2003.
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Yu-Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen, "Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264," Proc. IEEE International Symposium on Circuits and Systems(ISCAS 2003), Bangkok, Thailand, May 2003.
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Jen-Chieh Tuan, Tian-Sheuan Chang, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Transactions on circuits and systems for video technology, vol.12, no.1, Jan. 2002.
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CITED BY 11
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Zhenyu Liu , Yiqing Huang , Yang Song , Satoshi Goto , Takeshi Ikenaga, Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
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Yiqing Huang , Zhenyu Liu , Yang Song , Satoshi Goto , Takeshi Ikenaga, Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.4, p.987-997, April 2008
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Yiqing Huang , Qin Liu , Satoshi Goto , Takeshi Ikenaga, Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
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