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A variation-aware low-power coding methodology for tightly coupled buses
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Low power table of contents
Pages: 557 - 560  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Masanori Muroyama  Kyushu University, Fukuoka, Japan
Kosuke Tarumi  Kyushu University, Fukuoka, Japan
Koji Makiyama  Kyushu University, Fukuoka, Japan
Hiroto Yasuura  Kyushu University, Fukuoka, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumption on buses, in which the major sources of the power consumption are the transition activities on the signal lines and the coupling capacitances of the lines. In addition, we enter an era of considering variation of the effective coupling capacitances. We address power reduction including these phenomena by using variable length coding. Experimental results show the effectiveness of our methodology.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. Muroyama, A. Hyodo, T. Okuma and H. Yasuura, "A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits," IEICE Trans. Electron., vol. E87-C, No.4, pp.598--605, Apr. 2004.
 
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Collaborative Colleagues:
Masanori Muroyama: colleagues
Kosuke Tarumi: colleagues
Koji Makiyama: colleagues
Hiroto Yasuura: colleagues