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Studying interactions between prefetching and cache line turnoff
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Low power table of contents
Pages: 545 - 548  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Ismail Kadayif  Canakkale Onsekiz Mart University
Mahmut Kandemir  Pennsylvania State University
Guilin Chen  Pennsylvania State University
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance-oriented techniques influence energy behavior of the cache, and the energy-oriented techniques usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper studies this interaction and illustrates how performance and energy optimizations affect each other. We also point out several potential optimizations that could be based on this study.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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"Spec cpu2000 benchmark. http://www.spec.org/".
 
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D. C. Burger and T. M. Austin, "The SimpleScalar toolset, version 2.0," Tech. Rep. 1342, Dept. of Computer Science, UW, June 1997.
 
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K. K. Chan, "Design of the HP PA 7200 cpu", Hewlett-packard J., vol. 47, no. 1, pp. 25--33.
 
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J. Montenaro et al., "160 mHz 32b 0.5w CMOS RISC Microprocessor," in Proceedings of the International Solid State Circuits Conference, 1996.
 
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P. Shivakumar and N. P. Jouppi, "Cacti 3.0: an integrated cache timing, power, and area model," Technical Report, Digital Equipment Corporation, 1990.
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Collaborative Colleagues:
Ismail Kadayif: colleagues
Mahmut Kandemir: colleagues
Guilin Chen: colleagues