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Redundant-via enhanced maze routing for yield improvement
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Poster session III table of contents
Pages: 1148 - 1151  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Gang Xu  University of Texas at Austin, Austin, TX
Li-Da Huang  Texas Instruments, Austin, TX
David Z. Pan  University of Texas at Austin, Austin, TX
Martin D. F. Wong  University of Illinois at Urbana Champaign, Urbana, IL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 22,   Citation Count: 18
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ABSTRACT

Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with redundant via constraints. The problem is transformed to a multiple constraint shortest path problem, and solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing layout with much higher rate of redundant via than conventional maze routing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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TSMC Symposium 2004.
 
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G. A. Allan and A. J. Walto, "Automated redundant via placement for increased yield and reliability", Proc of SPIE, vol 3216, pp 114--125, 1997.
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CITED BY  18
Collaborative Colleagues:
Gang Xu: colleagues
Li-Da Huang: colleagues
David Z. Pan: colleagues
Martin D. F. Wong: colleagues