| Redundant-via enhanced maze routing for yield improvement |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Shanghai, China
SESSION: Poster session III
table of contents
Pages: 1148 - 1151
Year of Publication: 2005
ISBN:0-7803-8737-6
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Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 18
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ABSTRACT
Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with redundant via constraints. The problem is transformed to a multiple constraint shortest path problem, and solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing layout with much higher rate of redundant via than conventional maze routing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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TSMC Symposium 2004.
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G. A. Allan and A. J. Walto, "Automated redundant via placement for increased yield and reliability", Proc of SPIE, vol 3216, pp 114--125, 1997.
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CITED BY 18
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Huang-Yu Chen , Mei-Fang Chiang , Yao-Wen Chang , Lumdo Chen , Brian Han, Novel full-chip gridless routing considering double-via insertion, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Tsai-Ying Lin , Tsung-Han Lin , Hui-Hsiang Tung , Rung-Bin Lin, Double-via-driven standard cell library design, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Jeanne Bickford , Jason Hibbeler , Markus Buhler , Jurgen Koehl , Dirk Muller3 , Sven Peyer , Christian Schulte, Yield Improvement by Local Wiring Redundancy, Proceedings of the 7th International Symposium on Quality Electronic Design, p.473-478, March 27-29, 2006
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Jeanne Bickford , Jason Hibbeler , Markus Buhler , Jurgen Koehl , Dirk Muller3 , Sven Peyer , Christian Schulte, Yield Improvement by Local Wiring Redundancy, Proceedings of the 7th International Symposium on Quality Electronic Design, p.473-478, March 27-29, 2006
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Kuang-Yao Lee , Cheng-Kok Koh , Ting-Chi Wang , Kai-Yuan Chao, Optimal post-routing redundant via insertion, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
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Lun-Chun Wei , Hung-Ming Chen , Li-Da Huang , Sarah Songjie Xu, Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
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