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TERPS: the embedded reliable processing system
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: University design contest table of contents
Pages: 1 - 2  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Hongxia Wang  University of Maryland, College Park, College Park, MD
Samuel Rodriguez  University of Maryland, College Park, College Park, MD
Cagdas Dirik  University of Maryland, College Park, College Park, MD
Amol Gole  University of Maryland, College Park, College Park, MD
Vincent Chan  University of Maryland, College Park, College Park, MD
Bruce Jacob  University of Maryland, College Park, College Park, MD
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically checkpointing processor state into a special safe-storage device. The detection of EMI invokes rollback, which recovers processor state from a previously check-pointed state and resumes normal execution. Rollback results in loss of performance dictated by the EMI duration; TERPS ensures forward progress of the system provided EMI events are separated by some minimum time interval (e.g., at least 5.12μs for our prototype processor running at 100MHz). The performance overhead of our mechanism is reasonable: 5-6% overhead when check-pointing every 128 processor cycles.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Seevinck, E. et al, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no.5, pp.748--754, Oct. 1987.
 
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Ishibashi, K. et al, "An alpha-immune 2-V supply voltage SRAM using a polysilicon PMOS load cell," IEEE J. Solid-State Circuits vol SC-25, no.1, pp.55--60, Feb. 1990.
 
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Sato, H. et al, "A 500-MHz pipeline burst SRAM with improved SER immunity," IEEE J. Solid-State Circuits vol. SC-34, no. 11, pp. 1571--1579, Nov. 1999.
Collaborative Colleagues:
Hongxia Wang: colleagues
Samuel Rodriguez: colleagues
Cagdas Dirik: colleagues
Amol Gole: colleagues
Vincent Chan: colleagues
Bruce Jacob: colleagues