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ABSTRACT
In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this combination can be easily implemented in layouts with negligible design and manufacturing overhead. Our results show that power-delay characteristics of the achieved intermediate thresholds match well with the ideal (but impractical) scenario that assumes that all intermediate thresholds are available in the technology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
|
International Technology Roadmap for Semiconductors, 2003.
|
 |
2
|
|
| |
3
|
J. Tschanz et al, "Design Optimizations of a High-Performance Microprocessor using Combinations of Dual-Vt Allocation and Transistor Sizing," Intl. Symp. VLSI Circuits, pp. 218--219, 2002.
|
| |
4
|
Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999
[doi> 10.1109/92.748196]
|
| |
5
|
X. Huang et al, "Sub-50nm P-Channel FinFET," IEEE Trans on Electron Devices, vol. 48, pp. 880--886, 2001.
|
| |
6
|
S. Cristoloveanu, F. Allibert and A. Zaslavsky, "Double-gate MOSFETs: Performance and Technology Options," Intl Semiconductor Device Research Symposium, pp. 459--460, 2001.
|
 |
7
|
A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States
[doi> 10.1145/383082.383135]
|
| |
8
|
S. Thompson, I. Young, J. Greason and M. Bohr, "Dual Threshold Voltages and Substrate Bias: Keys to High-Performance Low-Power 0.1um Logic Designs," Intl. Symp. Technology, pp. 69--70, 1997.
|
| |
9
|
J. Tschanz et al, "Dynamic Sleep Transistor and Body Bias for Active Leakage Control of Microprocessors," IEEE Journal of Solid State Circuits, vol. 38. pp. 1838--1844, Nov 2003.
|
| |
10
|
|
 |
11
|
|
 |
12
|
Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
[doi> 10.1145/513918.514042]
|
| |
13
|
|
| |
14
|
T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584--594, Apr. 1990.
|
CITED BY
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S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
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