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Achieving continuous VT performance in a dual VT process
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Design optimization for high-performance digital circuits table of contents
Pages: 393 - 398  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Kanak Agarwal  University of Michigan
Dennis Sylvester  University of Michigan
David Blaauw  University of Michigan
Anirudh Devgan  IBM Research
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this combination can be easily implemented in layouts with negligible design and manufacturing overhead. Our results show that power-delay characteristics of the achieved intermediate thresholds match well with the ideal (but impractical) scenario that assumes that all intermediate thresholds are available in the technology.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Kanak Agarwal: colleagues
Dennis Sylvester: colleagues
David Blaauw: colleagues
Anirudh Devgan: colleagues