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On structure and suboptimality in placement
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Placement techniques table of contents
Pages: 331 - 336  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Satoshi Ono  FAIS
Patrick H. Madden  University of Kitakyushu
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 14,   Citation Count: 3
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ABSTRACT

Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we present a novel placement approach that successfully identifies regularity, and obtains placements that are superior to other "general purpose" methods. This method has been integrated into our Feng Shui 2.6 bisection-based placement tool.On experiments with the PEKO benchmarks, our results are within 32% of optimal for both the large and small suites. The largest example, with 2.1 million cells, can be completed in sixteen hours. The majority of our run time is during detail placement--global placement takes under three hours. The success of our method shows that it can find structure, even when the structure was not expected or intended.As part of this work, we have made a number of observations related to the nature of suboptimality in placement. These observations have shown that some neglected research areas have great potential, while problems that receive considerable attention are essentially adequately solved.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design, 2002.
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S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598):671--680, May 1983.
 
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J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 10(3):356--365, 1991.
 
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P. H. Madden. Reporting of standard cell placement results. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21(2):240--247, February 2002.
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Collaborative Colleagues:
Satoshi Ono: colleagues
Patrick H. Madden: colleagues