ACM Home Page
Please provide us with feedback. Feedback
Fast floorplanning by look-ahead enabled recursive bipartitioning
Full text PdfPdf (316 KB)
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Poster session II table of contents
Pages: 1119 - 1122  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 27,   Citation Count: 13
Additional Information:

abstract   references   cited by   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1120725.1120838
What is a DOI?

ABSTRACT

A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
2
3
4
 
5
J. Cong, M. Romesis, and J. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. Technical Report TR040043, Computer Science Dept., University of California, Los Angeles, 2004.
6
 
7
 
8
X. Hong, S. Dong, G. Huang, Y. Ma, Y. Cai, C. Cheng, and J. Gu. A Non-slicing Floorplanning Algorithm Using Corner Block List Topological Representation. In Proc. Design Automation Conf., pages 268--273, 1999.
9
10
 
11
 
12
S. Nakatake, K. Fujiyoshi, H. Mirata, and Y. Kajitani. Module Packing Based on the BSG-structure and IC Layout Applications. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 17, pages 519--530, 1998.
 
13
 
14
 
15
 
16

CITED BY  13
Collaborative Colleagues:
Jason Cong: colleagues
Michail Romesis: colleagues
Joseph R. Shinnerl: colleagues