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ABSTRACT
A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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2
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3
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Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337541]
|
 |
4
|
Jason Cong , Gabriele Nataneli , Michail Romesis , Joseph R. Shinnerl, An area-optimality study of floorplanning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
[doi> 10.1145/981066.981083]
|
| |
5
|
J. Cong, M. Romesis, and J. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. Technical Report TR040043, Computer Science Dept., University of California, Los Angeles, 2004.
|
 |
6
|
Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309928]
|
| |
7
|
|
| |
8
|
X. Hong, S. Dong, G. Huang, Y. Ma, Y. Cai, C. Cheng, and J. Gu. A Non-slicing Floorplanning Algorithm Using Corner Block List Topological Representation. In Proc. Design Automation Conf., pages 268--273, 1999.
|
 |
9
|
George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266273]
|
 |
10
|
|
| |
11
|
Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
|
| |
12
|
S. Nakatake, K. Fujiyoshi, H. Mirata, and Y. Kajitani. Module Packing Based on the BSG-structure and IC Layout Applications. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 17, pages 519--530, 1998.
|
| |
13
|
|
| |
14
|
|
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15
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16
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CITED BY 13
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Tung-Chieh Chen , Tien-Chang Hsu , Zhe-Wei Jiang , Yao-Wen Chang, NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Tony F. Chan , Jason Cong , Michalis Romesis , Joseph R. Shinnerl , Kenton Sze , Min Xie, mPL6: a robust multilevel mixed-size placement engine, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Aaron N. Ng , Igor L. Markov , Rajat Aggarwal , Venky Ramachandran, Solving hard instances of floorplacement, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Michael D. Moffitt , Aaron N. Ng , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Jarrod A. Roy , Aaron N. Ng , Rajat Aggarwal , Venky Ramachandran , Igor L. Markov, Solving modern mixed-size placement instances, Integration, the VLSI Journal, v.42 n.2, p.262-275, February, 2009
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