| Deriving a new efficient algorithm for min-period retiming |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Shanghai, China
SESSION: Poster session I
table of contents
Pages: 990 - 993
Year of Publication: 2005
ISBN:0-7803-8737-6
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Author
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Hai Zhou
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Northwestern University, Evanston, IL
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Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 3
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ABSTRACT
A new efficient algorithm is derived for the minimal period retiming problem by formal methods. Contrary to all previous algorithms, which used binary search to check feasibilities on a range of candidate periods, the derived algorithm checks the optimality of a current period directly. It is much simpler and more efficient than previous algorithms. Experimental results showed that it is even faster than ASTRA, an efficient heuristic algorithm. Since the derived algorithm is incremental by nature, it also opens the opportunity to be combined with other optimization techniques.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. De Micheli. Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 10(1):63--73, January 1991.
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G. Even, I. Y. Spillinger, and L. Stok. Retiming Revisited and Reversed. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 15(3):348--357, March 1996.
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R. W. Floyd. Assigning meanings to program. In Proc. Amer. Math. Soc. Symposia in Applied Mathematics, volume 19, pages 19--31, 1967.
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C. E. Leiserson and J. B. Saxe. Optimizing Synchronous Systems. Journal of VLSI and Computer Systems, 1(1):41--67, Spring 1983.
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C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1):5--35, 1991.
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S. S. Sapatnekar and R. B Deokar. Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE TCAD, 15(10):1237--1248, October 1996.
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H. Zhou and C. Lin. Retiming for wire pipelining in system-on-chip. IEEE TCAD, 23(9):1338--1345, September 2004.
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