ACM Home Page
Please provide us with feedback. Feedback
A multi-level transmission line network approach for multi-giga hertz clock distribution
Full text PdfPdf (167 KB)
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Clock, power grid and thermal analysis and optimization table of contents
Pages: 103 - 106  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Hongyu Chen  University of California, San Diego
Chung-Kuan Cheng  University of California, San Diego
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 23,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1120725.1120756
What is a DOI?

ABSTRACT

In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and mesh [2,15,18,19] were proposed to distribute the clock signal with a balanced H-tree and lock the skew using the shunt effect of the mesh. However, in multi-giga hertz regime, the RC model [15] of the mesh is no longer valid. The inductance effect of the mesh can even make the skew worse. In this paper, we investigate the use of a novel architecture which incorporates multiple level transmission line shunts to distribute global clock signal. We derive the analytical expression of the skew reduction contributed by the shunt of a transmission line with the length of an integral multiple of clock wavelength. Based on the analytical skew expression, we adopt convex programming techniques to optimize the wire widths of the multi-level transmission line network. Simulation results show that the multilevel network achieves below 4ps skew for 10GHz clock rate.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
F. E. Anderson, et al, The Core Clock System on the Next Generation Itanium#8482; Microprocessor, ISSCC 2002 Session 8.5.
 
2
N. Bindal, T. Kelly, N. Velastegul, and K. L. Wong, "Scalable sub-10ps Skew Global Clock Distribution for a 90nm Multi-GHz IA Microprocessor," ISSCC 2003, Session 19.7
 
3
D. Boning and S. Nassif, Models of Process Variations in Device and Interconnect, in Design of High Performance Microprocessor Circuits, Editors: A. Chandrakasan, W. Bowhill, F. Fox, IEEE Press, 2000
 
4
C. K. Cheng, et al, Interconnect Analysis and Synthesis, 2000, Wiley Interscience.
 
5
6
 
7
I. Galton, D. A. Towne, J. J. Rosenberg, and H. T. Jensen, "Clock Distribution Using Coupled Oscillators," ISCAS pp.
 
8
V. Gutnik and A. P. Chandrakasan, "Active GHz clock network using distributed PLLs," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1553--1560, Nov. 2001
 
9
 
10
M. Kamon, M. J. Tsuk, and J. K. White, FastHenry: A multipole-accelerated 3-d inductance extraction program. IEEE Trans. on Microwave Theory and Techniques, 42(9):1750--8, September 1994.
 
11
N. A. Kurd, et al, A Multigigahertz Clocking Scheme for the Pentium® 4 Microprocessor, IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, Nov. 2001 pp. 1647--53.
 
12
 
13
M. Mori et al., "A Multiple Level Network Approach for Clock Skew Minimization with Process Variations," UCSD Technical Report, CS2003--0756
14
 
15
M. Orshansky, L. Milor, P. Chen, K. Keutzer and C. Hu, Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuit, IEEE trans. on CAD, p.544--553; vol. 21, No. 5, May 2002
 
16
P. J. Restle, et al, A Clock Distribution Network for Microprocessors, IEEE Journal of Solid-State Circuits, Vol. 36, No. 5, May 2001 pp. 792--99.
 
17
P. J. Restle, et al, The Clock Distribution of the Power4 Microprocessor, ISSCC 2002, Session 8.4.
 
18
Collaborative Colleagues:
Hongyu Chen: colleagues
Chung-Kuan Cheng: colleagues