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A Huffman-based coding with efficient test application
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Test and DFT (1) table of contents
Pages: 75 - 78  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Michihiro Shintani  Hiroshima City University, Ozuka-higashi, Asaminami-ku, Hiroshima, Japan
Toshihiro Ohara  Hiroshima City University, Ozuka-higashi, Asaminami-ku, Hiroshima, Japan
Hideyuki Ichihara  Hiroshima City University, Ozuka-higashi, Asaminami-ku, Hiroshima, Japan
Tomoo Inoue  Hiroshima City University, Ozuka-higashi, Asaminami-ku, Hiroshima, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

Test compression / decompression method using variable length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding imposes slow test application, and consequently it requires large test application time in spite of its high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords, and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. Experimental results show that the proposed method can archieve small test application time while keeping high compression ratio.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Ichihara and T. Inoue, "A Test Decompression Scheme for Variable-Length Coding," Proc. DELTA, pp. 396--400, 2002.
 
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M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
 
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Proc. DAC, pp. 145--150, 2002.
Collaborative Colleagues:
Michihiro Shintani: colleagues
Toshihiro Ohara: colleagues
Hideyuki Ichihara: colleagues
Tomoo Inoue: colleagues