| Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs |
| Full text |
Pdf
(127 KB)
|
| Source
|
Asia and South Pacific Design Automation Conference
archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
table of contents
Shanghai, China
SESSION: Test and DFT (1)
table of contents
Pages: 65 - 70
Year of Publication: 2005
ISBN:0-7803-8737-6
|
|
Author
|
|
Jin-Fu Li
|
National Central University, Jungli, Taiwan, R.O.C.
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 0
|
|
|
ABSTRACT
With the increasing demand for high-performance networking application, network components such as network interfaces and routers are built in dedicated hardware modulars. Content addressable memories (CAMs) play an important role in the network components. Testing CAMs is very complicated due to their special structure. This paper presents an efficient March-like test algorithm for detecting the comparison faults of ternary CAMs based on the comparison fault models of binary CAMs. The test algorithm requires 5N Write operations, 2N Erase operations, and (3N + 2B) Compare operations for an N x B-bit TCAM.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
K.-J. Lin and C.-W. Wu, "Testing content-addressable memories using functional fault models and March-like algorithms", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577--588, May 2000.
|
| |
3
|
|
| |
4
|
|
| |
5
|
X. Du, S. M. Reddy, J. Rayhawk, and W. T. Cheng, "Testing delay faults in embedded CAMs", in IEEE Asian Test Symp. (ATS), Nov. 2003, pp. 378--383.
|
| |
6
|
S. R. Ramirez-Chavez, "Encoding don't cares in static and dynamic content addressable memories", IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 8, pp. 575--578, Aug. 1992.
|
| |
7
|
D. Wright and M. Sachdev, "Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories", in Proc. Int. Test Conf. (ITC), 2003.
|
| |
8
|
Inc. MOSAID Technologies, "The next generation of content addressable memories", http://www.mosaid.com/, 1999.
|
| |
9
|
Valerie Lines , Abdullah Ahmed , Peter Ma , Stanley Ma , Robert McKenzie , Hong-Seok Kim , Cynthia Mar, 66MHz 2.3M Ternary Dynamic Content Addressable Memory, Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, p.101, August 07-08, 2000
|
| |
10
|
R. Dekker, F. Beenker, and L. Thijssen, "A realistic fault model and test algorithm for static random access memories", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567--572, June 1990.
|
| |
11
|
|
| |
12
|
|
|