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ABSTRACT

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.

REFERENCES

• 1: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 2: Adrijean Adriahantenaina , Herve Charlery , Alain Greiner , Laurent Mortiez , Cesar Albenes Zeferino, SPIN: A Scalable, Packet Switched, On-Chip Micro-Network, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20070, March 03-07, 2003
• 3: Christopher J. Glass , Lionel M. Ni, The turn model for adaptive routing, Journal of the ACM (JACM), v.41 n.5, p.874-902, Sept. 1994 [doi>10.1145/185675.185682]
• 4: Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004 [doi>10.1016/j.vlsi.2004.03.003]
• 5: Whelihan, D. The NOCsim Simulator Users Guide. 2003. http://www.ece.cmu.edu/~djw2/NOCsim/NOCsim2.3.pdf.
• 6: http://www.opnet.com
• 7: Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar , Tiehan Lv, A Case Study in Networks-on-Chip Design for Embedded Video, Proceedings of the conference on Design, automation and test in Europe, p.20770, February 16-20, 2004
• 8: Sun, Y-R. et al. Simulation and Evaluation for a Network on Chip Architecture Using Ns-2, In: 20th IEEE Norchip Conference. 2002.
• 9: Kogel, T. et al. A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks. In: CODES/ISSS. 2003, pp. 7-- 12.
• 10: Jeremy Chan , Sri Parameswaran, NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture, Proceedings of the 17th International Conference on VLSI Design, p.717, January 05-09, 2004
• 11: Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Giuseppe Maruccia , Francesco Papariello, OCCN: A Network-On-Chip Modeling and Simulation Framework, Proceedings of the conference on Design, automation and test in Europe, p.30174, February 16-20, 2004
• 12: Santiago Gonzalez Pestana , Edwin Rijpkema , Andrei Rdulescu , Kees Goossens , Om Prakash Gangwal, Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach, Proceedings of the conference on Design, automation and test in Europe, p.20764, February 16-20, 2004
• 13: Vishak Venkatraman , Andrew Laffely , Jinwook Jang , Hempraveen Kukkamalla , Zhi Zhu , Wayne Burleson, NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France [doi>10.1145/966747.966762]
• 14: OCP-IP. Open Core Protocol Specification - Version 2.0. Available at: http://www.ocpip.org/.