| Communication-driven task binding for multiprocessor with latency insensitive network-on-chip |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Shanghai, China
SESSION: System level design methodology for network-on-chip
table of contents
Pages: 39 - 44
Year of Publication: 2005
ISBN:0-7803-8737-6
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Authors
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Liang-Yu Lin
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National Chiao Tung University, Hsinchu, Taiwan, ROC
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Cheng-Yeh Wang
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National Chiao Tung University, Hsinchu, Taiwan, ROC
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Pao-Jui Huang
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National Chiao Tung University, Hsinchu, Taiwan, ROC
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Chih-Chieh Chou
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National Chiao Tung University, Hsinchu, Taiwan, ROC
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Jing-Yang Jou
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National Chiao Tung University, Hsinchu, Taiwan, ROC
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Downloads (6 Weeks): 14, Downloads (12 Months): 45, Citation Count: 1
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ABSTRACT
Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Adrijean Adriahantenaina , Herve Charlery , Alain Greiner , Laurent Mortiez , Cesar Albenes Zeferino, SPIN: A Scalable, Packet Switched, On-Chip Micro-Network, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20070, March 03-07, 2003
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3
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Partha Pratim Pande, Cristian Grecu, Andre Ivanov and Res Saleh, "Design of a switch for network on chip applications," in Proceedings of the 2003 International Symposium on Circuits and Systems, volume 5, pp. 217 -- 220, 2003.
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5
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6
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Danial M. Chapiro, "Globally-Asynchronous Locally-Synchronous Systems," PH.D. thesis, Stanford University, Oct. 1984.
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7
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8
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9
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Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku and Hideharu Amano, "BLACK-BUS: a new data-transfer technique using local address on networks-on-chips," in Proceedings of the 18th International Parallel and Distributed Processing Symposium, pp. 10 -- 17, 2004.
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10
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11
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Luca P. Carloni , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.309-315, November 07-11, 1999, San Jose, California, United States
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12
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|
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13
|
|
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14
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 |
15
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 |
16
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Alexander Marquardt , Vaughn Betz , Jonathan Rose, Timing-driven placement for FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.203-213, February 10-11, 2000, Monterey, California, United States
[doi> 10.1145/329166.329208]
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17
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18
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C. Y. Lee, "An algorithm for path connections and its applications," in IRE Transactions Electron Computing, volume EC 10, pp. 346 -- 365, 1961.
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19
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E. Dijkstra, "A Note on Two Problems in Connexion with Graphs," in Numerical Math, volume 1, pp. 269 -- 271, 1959.
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20
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21
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Robert P. Dick , David L. Rhodes , Wayne Wolf, TGFF: task graphs for free, Proceedings of the 6th international workshop on Hardware/software codesign, p.97-101, March 15-18, 1998, Seattle, Washington, United States
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CITED BY
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Terrence Mak , Crescenzo D'Alessandro , Pete Sedcole , Peter Y. K. Cheung , Alex Yakovlev , Wayne Luk, Global interconnections in FPGAs: modeling and performance analysis, Proceedings of the 2008 international workshop on System level interconnect prediction, April 05-08, 2008, Newcastle, United Kingdom
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