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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: System level design methodology for network-on-chip table of contents
Pages: 39 - 44  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Liang-Yu Lin  National Chiao Tung University, Hsinchu, Taiwan, ROC
Cheng-Yeh Wang  National Chiao Tung University, Hsinchu, Taiwan, ROC
Pao-Jui Huang  National Chiao Tung University, Hsinchu, Taiwan, ROC
Chih-Chieh Chou  National Chiao Tung University, Hsinchu, Taiwan, ROC
Jing-Yang Jou  National Chiao Tung University, Hsinchu, Taiwan, ROC
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Partha Pratim Pande, Cristian Grecu, Andre Ivanov and Res Saleh, "Design of a switch for network on chip applications," in Proceedings of the 2003 International Symposium on Circuits and Systems, volume 5, pp. 217 -- 220, 2003.
 
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Danial M. Chapiro, "Globally-Asynchronous Locally-Synchronous Systems," PH.D. thesis, Stanford University, Oct. 1984.
 
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Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku and Hideharu Amano, "BLACK-BUS: a new data-transfer technique using local address on networks-on-chips," in Proceedings of the 18th International Parallel and Distributed Processing Symposium, pp. 10 -- 17, 2004.
 
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C. Y. Lee, "An algorithm for path connections and its applications," in IRE Transactions Electron Computing, volume EC 10, pp. 346 -- 365, 1961.
 
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E. Dijkstra, "A Note on Two Problems in Connexion with Graphs," in Numerical Math, volume 1, pp. 269 -- 271, 1959.
 
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Collaborative Colleagues:
Liang-Yu Lin: colleagues
Cheng-Yeh Wang: colleagues
Pao-Jui Huang: colleagues
Chih-Chieh Chou: colleagues
Jing-Yang Jou: colleagues