| Making fast buffer insertion even faster via approximation techniques |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Shanghai, China
SESSION: Tree construction and buffering
table of contents
Pages: 13 - 18
Year of Publication: 2005
ISBN:0-7803-8737-6
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Authors
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Zhuo Li
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Texas A&M University, College Station, TX
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C. N. Sze
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Texas A&M University, College Station, TX
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Charles J. Alpert
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IBM Austin Research Lab, Austin, TX
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Jiang Hu
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Texas A&M University, College Station, TX
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Weiping Shi
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Texas A&M University, College Station, TX
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Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 8
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ABSTRACT
As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing electrical violations. Consequently, buffer insertion is needed on tens of thousands of nets during physical synthesis optimization. Even the fast implementation of van Ginneken's algorithm requires several hours to perform this task. This work seeks to speed up the van Ginneken style algorithms by an order of magnitude while achieving similar results. To this end, we present three approximation techniques in order to speed up the algorithm: (1) aggressive pre-buffer slack pruning, (2) squeeze pruning, and (3) library lookup. Experimental results from industrial designs show that using these techniques together yields solutions in 9 to 25 times faster than van Ginneken style algorithms, while only sacrificing less than 3% delay penalty.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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W. Shi and Z. Li, "A Fast Algorithm for Fast Buffer Insertion," IEEE Trans. CAD, to appear.
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CITED BY 8
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C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Path based buffer insertion, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Yu Hu , King Ho Tam , Tom Tong Jing , Lei He, Fast dual-vdd buffering based on interconnect prediction and sampling, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
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Zhuo Li , Charles J. Alpert , Shiyan Hu , Tuhin Muhmud , Stephen T. Quay , Paul G. Villarrubia, Fast interconnect synthesis with layer assignment, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
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