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Making fast buffer insertion even faster via approximation techniques
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Tree construction and buffering table of contents
Pages: 13 - 18  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Zhuo Li  Texas A&M University, College Station, TX
C. N. Sze  Texas A&M University, College Station, TX
Charles J. Alpert  IBM Austin Research Lab, Austin, TX
Jiang Hu  Texas A&M University, College Station, TX
Weiping Shi  Texas A&M University, College Station, TX
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 18,   Citation Count: 8
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ABSTRACT

As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing electrical violations. Consequently, buffer insertion is needed on tens of thousands of nets during physical synthesis optimization. Even the fast implementation of van Ginneken's algorithm requires several hours to perform this task. This work seeks to speed up the van Ginneken style algorithms by an order of magnitude while achieving similar results. To this end, we present three approximation techniques in order to speed up the algorithm: (1) aggressive pre-buffer slack pruning, (2) squeeze pruning, and (3) library lookup. Experimental results from industrial designs show that using these techniques together yields solutions in 9 to 25 times faster than van Ginneken style algorithms, while only sacrificing less than 3% delay penalty.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "Repeater scaling and its impact on cad," IEEE Trans. CAD, vol. 23, no. 4, pp. 451--463, 2004.
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L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree network for minimal elmore delay," in ISCAS, 1990, pp. 865--868.
 
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W. Shi and Z. Li, "A Fast Algorithm for Fast Buffer Insertion," IEEE Trans. CAD, to appear.
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J. Lillis, C. K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Trans. Solid-State Circuits, vol. 31, no. 3, pp. 437--447, 1996.
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J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, "Buffer insertion with adaptive blokage avoidance," IEEE Trans. CAD, vol. 22, no. 4, pp. 492--498, 2003.
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CITED BY  8
Collaborative Colleagues:
Zhuo Li: colleagues
C. N. Sze: colleagues
Charles J. Alpert: colleagues
Jiang Hu: colleagues
Weiping Shi: colleagues