Design at the end of the silicon roadmap

ABSTRACT

Scaling of silicon integrated technology into the deep sub-100 nm space brings with it a number of formidable challenges to the designer. Issues such as design complexity, power dissipation, process variability and reliability are challenging the traditional design methodologies. In this presentation, it is conjectured that the only viable long-term solution to these challenges is to drastically revise the way we do design, and a roadmap of potential solutions is presented. Ultimately, these innovative design solutions will help to pave the way to the post-silicon era.

REFERENCES

• 1: {Gelsinger04} P. Gelsinger, "GigaScale Integration for Teraops Performance -- Challenges, Opportunities, and New Frontiers," Keynote presentation 41st Design Automation Conference, http://videos.dac.com/41st/slides/TueKey.ppt, San Diego, June 2004.
• 2: {GSRC04} The MARCO Gigascale Systems Research Center, http://www.gigascale.org.
• 3: {ITRS03} The 2003 International Technology Roadmap for Semiconductors, http://public.itrs.net/Files/2003ITRS/Home2003.htm
• 4: {Sakurai03} T. Sakurai, "Perspectives on Power-Aware Electronics," Keynote presentation 2003 ISSCC Conference, Visual Supplements, pp 14--15, San Francisco, February 2003.