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Silicon compilation: the answer to reducing IC development costs
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
Shanghai, China
SESSION: Keynote address table of contents
Pages: 1 - 2  
Year of Publication: 2005
ISBN:0-7803-8737-6
Author
Rajeev Madhavan  CEO of Magma Design Automation
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

Developing today's increasingly large and complex digital integrated circuit (IC) and system-on-chip (SoC) devices is becoming cost-prohibitive in terms of engineering resources and development time. Packing the advanced functionality of a microprocessor, a graphics processor, or a network controller into a silicon die just 18 millimeters on a side is a complex undertaking that can require a 50-person engineering team and up to 4 million lines of HDL code. In these complex designs managing and minimizing power is becoming a huge challenge. Meanwhile, the cost of the mask set needed to drive the semiconductor production equipment stands at more than $1 million. Errors found after the mask set is created increase costs by an additional $1 million or more.