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ABSTRACT
The rectilinear Steiner minimum tree (RSMT) problem, which asks for a minimum-length interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle nets with tens of thousands of terminals. In this paper we give a practical O (n log2 n) heuristic for computing near-optimal rectilinear Steiner trees based on a batched version of the greedy triple contraction algorithm of Zelikovsky [21]. Experiments conducted on both random and industry testcases show that our heuristic matches or exceeds the quality of best known RSMT heuristics, e.g., on random instances with more than 100 terminals our heuristic improves over the rectilinear minimum spanning tree by an average of 11%. Moreover, our heuristic has very well scaling runtime, e.g., it can route a 34k-terminals net extracted from a real design in less than 25 seconds compared to over 86 minutes needed by the O(n2) edge-based heuristic of Borah, Owens, and Irwin [3]. Since our heuristic is graph-based, it can be easily modified to handle practical considerations such as routing obstacles, preferred directions, via costs, and octilinear routing - indeed, experimental results show only a small factor increase in runtime when switching from rectilinear to octilinear routing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 18
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Weixiang Shen , Yici Cai , Xianlong Hong , Jiang Hu , Bing Lu, Zero skew clock routing in X-architecture based on an improved greedy matching algorithm, Integration, the VLSI Journal, v.41 n.3, p.426-438, May, 2008
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Qi Zhu , Hai Zhou , Tong Jing , Xianlong Hong , Yang Yang, Efficient octilinear Steiner tree construction based on spanning graphs, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.687-690, January 27-30, 2004, Yokohama, Japan
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Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion Mandoiu , Qinke Wang, Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
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Tsung-Yi Ho , Chen-Feng Chang , Yao-Wen Chang , Sao-Jie Chen, Multilevel full-chip routing for the X-based architecture, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Yin Wang , Xianlong Hong , Tong Jing , Yang Yang , Xiaodong Hu , Guiying Yan, The polygonal contraction heuristic for rectilinear Steiner tree construction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Hsin-Hsiung Huang , Hui Yu Huang , De-Jing Huang , Tsai-Ming Hsieh, An efficient rectilinear Steiner tree algorithm with obstacles, Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing, p.54-59, November 01-03, 2006, Dallas, Texas
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Yiyu Shi , Paul Mesa , Hao Yu , Lei He, Circuit simulation based obstacle-aware Steiner routing, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion Mandoiu , Qinke Wang , Bo Yao, The Y-Architecture for On-Chip Interconnect: Analysis and Methodology, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.13, November 09-13, 2003
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Hsin-Hsiung Huang , Shu-Ping Chang , Yu-Cheng Lin , Tsai-Ming Hsieh, Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture, Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems, p.31-34, May 20-22, 2009, Hangzhou, China
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