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Integer linear programming-based synthesis of skewed logic circuits
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2003 Asia and South Pacific Design Automation Conference table of contents
Kitakyushu, Japan
SESSION: Synthesis for power performance optimization table of contents
Pages: 820 - 823  
Year of Publication: 2003
ISBN:0-7803-7660-9
Authors
Aiqun Cao  Purdue University
Naran Sirisantana  Purdue University
Cheng-Kok Koh  Purdue University
Kaushik Roy  Purdue University
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
Publisher
ACM  New York, NY, USA
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ABSTRACT

We present an integer linear programming-based approach for solving the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. A simplification technique is applied to reduce the complexity of the ILP problem greatly so that the run time is more affordable. Experimental results show that an average of 18% of original gates are duplicated in skewed logic circuits, whereas 65% in Domino logic circuits are duplicated. The average power saving over Domino logic circuits is 40.9%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. R. Prasad, D. Kirkpatrick, R. K. Brayton, and A. Sangiovanni-Vincentelli. Domino logic synthesis and technology mapping. In Proc. Int. Workshop on Logic Synthesis, May 1997.
 
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M. Zhao and S. S. Sapatnekar. Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 309--312, May 2000.

Collaborative Colleagues:
Aiqun Cao: colleagues
Naran Sirisantana: colleagues
Cheng-Kok Koh: colleagues
Kaushik Roy: colleagues