Floorplanning with power supply noise avoidance

ABSTRACT

With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.

REFERENCES

• 1: "International Technology Roadmap for Semiconductor". 1997.
• 2: Ravindra K. Ahuja , Thomas L. Magnanti , James B. Orlin, Network flows: theory, algorithms, and applications, Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
• 3: G. Bai , S. Bobba , I. N. Hajj, Simulation and optimization of the power distribution network in VLSI circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 4: H. B. Bakoglu. "Circuits, Interconnections, and Packaging for VLSI". Addison Wesley, 1990.
• 5: P. H. Buffet, J. Natonio, R. A. Proctor, Y. H. Sun, and G. Yasar. "Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid". In IEEE Custom Integrated Circuits Conference, pages 125--128, 2000.
• 6: K.-Y. Chao and D. F. Wong. "Floorplan Design with Low Power Considerations". Selected Topics in Electronic and Systems, 6:83--100, 1996.
• 7: Hung-Ming Chen , Hai Zhou , F. Y. YOung , D. F. Wong , Hannah H. Yang , Naveed Sherwani, Integrated floorplanning and interconnect planning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.354-357, November 07-11, 1999, San Jose, California, United States
• 8: Howard H. Chen , David D. Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of the 34th annual conference on Design automation, p.638-643, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266307]
• 9: J. Cong. "An Interconnect-Centric Design Flow for Nanometer Technologies". Proceedings of the IEEE, 89(4):505--528, April 2001.
• 10: Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
• 11: John F. Croix. "The Need for Accurate Power Models for Deep Submicron IP reuse". Electronic Systems, 1999.
• 12: L. Liang, J. D. Wilson, N. Brathwaite, L. E. Mosley, and D. Love. "High-Performance VLSI Through Package-Level Interconnects". In Proceedings of the 39th Electron. Components Conf., pages 518--523, 1989.
• 13: I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan [doi>10.1145/370155.370539]
• 14: Joel Mcgrath. "Chip/Package co-design: The bridge between chips and systems". In Advanced Packaging, June 2001.
• 15: Farid N. Najm. "Low-Power Design Methodology: Power Estimation and Optimization". In Proceedings of the 40th Midwest Symposium on Circuits and Systems, pages 1124--1129, 1997.
• 16: K. T. Tang and E. G. Friedman. "On-Chip Delta-I Noise in the Power Distribution Networks of High Speed CMOS Integrated Circuits". In IEEE ASIC/SOC Conference, pages 53--57, 2000.
• 17: D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
• 18: M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. Blaauw. "Hierarchical Analysis of Power Distribution Networks". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(2):159--168, February 2002.
• 19: Shiyou Zhao , Kaushik Roy , Cheng-Kok Koh, Decoupling capacitance allocation for power supply noise suppression, Proceedings of the 2001 international symposium on Physical design, p.66-71, April 01-04, 2001, Sonoma, California, United States [doi>10.1145/369691.369737]