| Multi-level placement for large-scale mixed-size IC designs |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2003 Asia and South Pacific Design Automation Conference
table of contents
Kitakyushu, Japan
SESSION: Modeling for floorplan
table of contents
Pages: 325 - 330
Year of Publication: 2003
ISBN:0-7803-7660-9
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Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 28
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ABSTRACT
In this paper we study the large-scale mixed-size placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multi-level optimization algorithm, MPGMS, for this problem which can efficiently handle both large-scale designs and large size variations. Compared with the recently published work [1] on large-scale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13% wirelength reduction on average with comparable runtime.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518--1524, 1996.
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Michael Upton , Khosrow Samii , Stephen Sugiyama, Integrated placement for mixed macro cell and standard cell designs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.32-35, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123219]
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A. Shanbhag, S. Danda, and N. Sherwani, "Floorplanning for mixed macro block and standard cell designs," in Proc. the forth Great Lakes Symp. on VLSI, pp. 26--29, 1994.
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J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, pp. 505--527, April 2001.
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C. Sechen and A. Sangiovanni-Vincentelli, "The Timberwolf placement and routing package," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 510--522, 1985.
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W. J. Sun and C. Sechen, "Efficient and effective placement for very large circuits," in Proc. Int. Conf. on Computer Aided Design, pp. 336--339, 1990.
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B. S. Baker, E. G. Coffman, and R. L. Rivest, "Orthogonal packings in two dimensions," SIAM J. Compute., vol. 9, no. 4, pp. 846--855, 1980.
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CITED BY 28
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Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Nan-Chi Chou , Lung-Tien Liu , Peter Suaris, Unified quadratic programming approach for mixed mode placement, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Tung-Chieh Chen , Tien-Chang Hsu , Zhe-Wei Jiang , Yao-Wen Chang, NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Ateen Khatkhate , Chen Li , Ameya R. Agnihotri , Mehmet C. Yildiz , Satoshi Ono , Cheng-Kok Koh , Patrick H. Madden, Recursive bisection based mixed block placement, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
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Zhe-Wei Jiang , Tung-Chieh Cheny , Tien-Chang Hsuy , Hsin-Chen Chenz , Yao-Wen Changyz, NTUplace2: a hybrid placer using partitioning and analytical techniques, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Aaron N. Ng , Igor L. Markov , Rajat Aggarwal , Venky Ramachandran, Solving hard instances of floorplacement, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Michael D. Moffitt , Aaron N. Ng , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Tung-Chieh Chen , Zhe-Wei Jiang , Tien-Chang Hsu , Hsin-Chen Chen , Yao-Wen Chang, A high-quality mixed-size analytical placer considering preplaced blocks and density constraints, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
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S. N. Adya , S. Chaturvedi , J. A. Roy , D. A. Papa , I. L. Markov, Unification of partitioning, placement and floorplanning, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.550-557, November 07-11, 2004
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Tung-Chieh Chen , Ping-Hung Yuh , Yao-Wen Chang , Fwu-Juh Huang , Denny Liu, MP-trees: a packing-based macro placement algorithm for mixed-size designs, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
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Jarrod A. Roy , Aaron N. Ng , Rajat Aggarwal , Venky Ramachandran , Igor L. Markov, Solving modern mixed-size placement instances, Integration, the VLSI Journal, v.42 n.2, p.262-275, February, 2009
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