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Multi-level placement for large-scale mixed-size IC designs
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2003 Asia and South Pacific Design Automation Conference table of contents
Kitakyushu, Japan
SESSION: Modeling for floorplan table of contents
Pages: 325 - 330  
Year of Publication: 2003
ISBN:0-7803-7660-9
Authors
Chin-Chih Chang  University of California, Los Angeles, CA
Jason Cong  University of California, Los Angeles, CA
Xin Yuan  University of California, Los Angeles, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 18,   Citation Count: 28
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ABSTRACT

In this paper we study the large-scale mixed-size placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multi-level optimization algorithm, MPGMS, for this problem which can efficiently handle both large-scale designs and large size variations. Compared with the recently published work [1] on large-scale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13% wirelength reduction on average with comparable runtime.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518--1524, 1996.
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A. Shanbhag, S. Danda, and N. Sherwani, "Floorplanning for mixed macro block and standard cell designs," in Proc. the forth Great Lakes Symp. on VLSI, pp. 26--29, 1994.
 
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J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, pp. 505--527, April 2001.
 
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C. Sechen and A. Sangiovanni-Vincentelli, "The Timberwolf placement and routing package," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 510--522, 1985.
 
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W. J. Sun and C. Sechen, "Efficient and effective placement for very large circuits," in Proc. Int. Conf. on Computer Aided Design, pp. 336--339, 1990.
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B. S. Baker, E. G. Coffman, and R. L. Rivest, "Orthogonal packings in two dimensions," SIAM J. Compute., vol. 9, no. 4, pp. 846--855, 1980.
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CITED BY  28
Collaborative Colleagues:
Chin-Chih Chang: colleagues
Jason Cong: colleagues
Xin Yuan: colleagues