Energy-aware mapping for tile-based NoC architectures under performance constraints

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Energy-aware mapping for tile-based NoC architectures under performance constraints

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2003 Asia and South Pacific Design Automation Conference table of contents

Kitakyushu, Japan

SESSION: SoC and NoC table of contents

Pages: 233 - 239

Year of Publication: 2003

ISBN:0-7803-7660-9

Authors

Jingcao Hu	Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu	Carnegie Mellon University, Pittsburgh, PA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 130, Citation Count: 61

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abstract references cited by collaborative colleagues

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ABSTRACT

In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.

REFERENCES

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Collaborative Colleagues:

Jingcao Hu: colleagues

Radu Marculescu: colleagues

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