Abridged addressing: a low power memory addressing strategy

ABSTRACT

The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the sequence of addresses appearing on the memory address bus as well as the switching activity in the addressing logic, has a major impact on the memory subsystem power dissipation. We present a novel addressing strategy, Abridged Addressing, that helps reduce system power dissipation by substantially reducing both the address bus switching as well the addressing logic power. The strategy, which relies on minimizing register accesses in the addressing logic, helps overcome some of the limitations of existing approaches: the address bus switching is low; there is very little area, performance, and power overhead; and the addressing hardware is simpler, making the technique suitable for both on-chip and off-chip memory, as well as single-port and multi-port memories.

REFERENCES

• 1: Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
• 2: Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
• 3: Ching-Long Su , Alvin M. Despain, Cache design trade-offs for power and performance optimization: a case study, Proceedings of the 1995 international symposium on Low power design, p.63-68, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224093]
• 4: Luca Benini , Giovanni de Micheli, Dynamic Power Management: Design Techniques and CAD Tools, Kluwer Academic Publishers, Norwell, MA, 1998
• 5: Enric Musoll , Tomás Lang , Jordi Cortadella, Working-zone encoding for reducing the energy in microprocessor address buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.568-572, Dec. 1998 [doi>10.1109/92.736129]
• 6: Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.212-221, June 1999 [doi>10.1109/92.766748]
• 7: Luca Benini , Giovanni De Mecheli , Enrico Macii , Massimo Poncino , Stefano Quer, Power optimization of core-based systems by address bus encoding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.554-562, Dec. 1998 [doi>10.1109/92.736127]
• 8: Mahesh Mamidipaka , Dan Hirschberg , Nikil Dutt, Low power address encoding using self-organizing lists, Proceedings of the 2001 international symposium on Low power electronics and design, p.188-193, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383129]
• 9: Luca Benini , Alberto Macii , Massimo Poncino, A recursive algorithm for low-power memory partitioning, Proceedings of the 2000 international symposium on Low power electronics and design, p.78-83, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344518]
• 10: Precti Ranjan Panda , Nikil D. Dutt, Low-power memory mapping through reducing address bus activity, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.309-320, Sept. 1999 [doi>10.1109/92.784092]
• 11: Peter Petrov , Alex Orailoglu, Low-power data memory communication for application-specific embedded processors, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581248]
• 12: Khurram Muhammad , Kaushik Roy, A novel design methodology for high performance and low power digital filters, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.80-83, November 07-11, 1999, San Jose, California, United States
• 13: E. Lawler, Combinatorial optimization: networks and matroids, Saunders College Publishing, Cambridge, MA, 1976.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.m Miscellaneous
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance