Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

ABSTRACT

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

General Terms:
Design, Performance, Theory

Keywords:
64-bit Power Architecture, CELL Processor, Linux, SOC, SOI, clock distribution, correct-by-construction, design dependency solution, design environment, design hierarchy, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, modularity, multi-core, multi-operating system, multi-threading, power management, re-use, real-time system, synergistic processor, thermal management, virtualization technology