An SPU reference model for simulation, random test generation and verification

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An SPU reference model for simulation, random test generation and verification

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: Designers' forum: "cell" processor table of contents

Pages: 860 - 866

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Yukio Watanabe	Toshiba Corporation, Horikawa-Cho, Saiwai-Ku, Kawasaki, Japan
Balazs Sallay	IBM, Austin, TX
Brad Michael	IBM, Austin, TX
Daniel Brokenshire	IBM, Austin, TX
Gavin Meil	IBM, Austin, TX
Hazim Shafi	IBM, Austin, TX
Daisuke Hiraoka	Sony Computer Entertainment Inc., Minami-Aoyama, Minato-ku, Tokyo, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 16, Citation Count: 1

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ABSTRACT

An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [1][2]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pham D. et al, "The Design and Implementation of a First-eneration CELL Processor," 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 184--185, Feb. 2005.
	2	Flachs B. et al, "A streaming Processing Unit for a CELL Processor," 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 134--135, Feb. 2005
	3	Allon Adir , Eli Almog , Laurent Fournier , Eitan Marcus , Michal Rimon , Michael Vinov , Avi Ziv, Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification, IEEE Design & Test, v.21 n.2, p.84-93, March 2004 [doi>10.1109/MDT.2004.1277900]
	4	Patrick Bohrer , James Peterson , Mootaz Elnozahy , Ram Rajamony , Ahmed Gheith , Ron Rockhold , Charles Lefurgy , Hazim Shafi , Tarun Nakra , Rick Simpson , Evan Speight , Kartik Sudeep , Eric Van Hensbergen , Lixin Zhang, Mambo: a full system simulator for the PowerPC architecture, ACM SIGMETRICS Performance Evaluation Review, v.31 n.4, p.8-12, March 2004 [doi>10.1145/1054907.1054910]