A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers

ABSTRACT

As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M), or 1 poly with 5 metal layers (1P5M). Dies with different desired manufacturing processes cannot be produced from the same wafer, but they can be put onto the same set of masks in order to reduce the total cost of the used masks and wafers. In this paper, we propose a novel integer linear programming (ILP)-based floorplanner for shuttle runs consisting of projects requiring different desired processes. Two simulated annealing-based side-to-side wafer dicing planners are also presented. Experimental results show that our approach achieves 28% wafer reduction on average compared to a previous simulated annealing-based reticle floorplanner.

REFERENCES

• 1: Warren Grobman , Robert Boone , Cece Philbin , Bob Jarvis, Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs, Proceedings of the 2001 international symposium on Physical design, p.45-51, April 01-04, 2001, Sonoma, California, United States [doi>10.1145/369691.369730]
• 2: John, and B. Lin, "Mask Cost and Cycle Time Reduction" http://www.sematech.org/resources/litho/meetings/mask/20011001/E_TSMC.PDF
• 3: C. Yang, "Challenges of Mask Cost & Cycle Time" http://www.sematech.org/resources/litho/meetings/mask/20011001/K_Mask_cost_Intel.pdf
• 4: S. Chen and E. C. Lynn, "Efficient Placement of Chips on a Shuttle Mask", in Proc. of SPIE, Vol. 5130, 2003, pp.681--688.
• 5: M. Andersson, C. Levcopoulos, and J. Gudmundsson, "Chips on Wafers" in Proc. Workshop on Algorithms and Data Structures, 2003.
• 6: G. Xu, R. Tian, D. F. Wang, and A. Reich "Shuttle Mask Floorplanning" in Proc. of SPIE, Vol. 5256, 2003, pp.185--194.
• 7: A. B. Kahng, I. Mandoiu, Q. Wang, X. Xu, and A. Zelikovsky, "Multi-Project Reticle Floorplanning and Wafer Dicing" in Proc. of ACM/IEEE on ISPD, 2004, pp. 70--77.
• 8: G. Xu, R. Tian, D. Z. Pan, and D. F. Wang "A Multiple-objective Floorplanner for Shuttle Mask Optimization" in Proc. of SPIE, Vol. 5567, 2004, pp.185--144.
• 9: Andrew B. Kahng , Sherief Reda, Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.106-110, October 11-13, 2004
• 10: Meng-Chiou Wu , Rung-Bin Lin, Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.610-615, March 21-23, 2005 [doi>10.1109/ISQED.2005.106]
• 11: Global UniChip Corp. http://www.globalunichip.com/
• 12: M. Berkelaar, K. Eikland, P. Notebaert, lp_solve, available from http://groups.yahoo.com.tw/group/lp_solve

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.2 Design Aids
          Subjects: Layout
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS
      G.1.6 Optimization
          Subjects: Linear programming; Integer programming

General Terms:
Algorithms, Design, Performance