Speed binning aware design methodology to improve profit under parameter variations

ABSTRACT

Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve the profitability of design over an initial yield-optimized design. We also propose an algorithm to determine optimal bin boundaries for maximizing profit with frequency binning. Finally, we present an integrated design methodology for simultaneous sizing and bin placement to enhance profit under an area constraint. Experiments on a set of ISCAS85 benchmarks show up to 26% (36%) improvement in profit for fixed bin (for simultaneous sizing and bin placement) with three frequency bins considering both leakage and delay bounds compared to a design optimized for 90% yield at iso-area.

REFERENCES

• 1: K. A. Bowman et al., "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration", JSSC, 2002, pp. 183--190.
• 2: Liang-Chi Chen , S. K. Gupta , M. A. Breuer, A new framework for static timing analysis, incremental timing refinement, and timing simulation, Proceedings of the 9th Asian Test Symposium, p.102, December 04-06, 2000
• 3: Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]
• 4: Bruce D. Cory , Rohit Kapur , Bill Underwood, Speed Binning with Path Delay Test in 150-nm Technology, IEEE Design & Test, v.20 n.5, p.41-45, September 2003 [doi>10.1109/MDT.2003.1232255]
• 5: Rajeev R. Rao , Anirudh Devgan , David Blaauw , Dennis Sylvester, Parametric yield estimation considering leakage variability, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996693]
• 6: Seung Hoon Choi , Bipul C. Paul , Kaushik Roy, Novel sizing algorithm for yield improvement under process variation in nanometer technology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996695]
• 7: Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289097]
• 8: Kunhyuk Kang , Bipul C. Paul , Kaushik Roy, Statistical Timing Analysis using Levelized Covariance Propagation, Proceedings of the conference on Design, Automation and Test in Europe, p.764-769, March 07-11, 2005 [doi>10.1109/DATE.2005.279]
• 9: "Technology Models", http://www-device.eecs.berkeley.edu/~ptm.
• 10: Aseem Agarwal , Kaviraj Chopra , David Blaauw , Vladimir Zolotov, Circuit optimization using statistical static timing analysis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065663]
• 11: T. Sakurai et al., "Delay Analysis of Series-connected MOSFET Circuits", IEEE JSSC, vol. 26, no. 2, 1991, pp. 122--131.
• 12: Xin Li , Jiayong Le , P. Gopalakrishnan , L. T. Pileggi, Asymptotic probability extraction for non-normal distributions of circuit performance, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.2-9, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382533]
• 13: Xiaoliang Bai , Chandu Visweswariah , Philip N. Strenski, Uncertainty-aware circuit optimization, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513935]
• 14: "Processor Retail prices", http://www.newegg.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance