Statistical corner conditions of interconnect delay (corner LPE specifications)

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Statistical corner conditions of interconnect delay (corner LPE specifications)

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: Statistical and yield analysis table of contents

Pages: 706 - 711

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Kenta Yamada	NEC Electronics Corporation, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, Japan
Noriaki Oda	NEC Electronics Corporation, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 15, Citation Count: 2

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ABSTRACT

Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. In this paper, statistical corner conditions using the independence of variations between process parameters and between interconnect layers are proposed. As a result, the fast-to-slow guardband decreases by half in average, compared to the conventional method. The proposed method is ready for implementation to LPE tools.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Takahashi, Tech. Dig. IEDM, 1998, p.833--836
	2	K. Yamada, VLSI Tech. Dig., 2003, p.111--112
	3	S. Inoue, Japanese patent pending, No. P2001-265826A
	4	A. Kuroda, Workshop on Circuits and Systems in Karuizawa, 2005, p.25--30

CITED BY 2

	Takayuki Fukuoka , Akira Tsuchiya , Hidetoshi Onodera, Worst-case delay analysis considering the variability of transistors and interconnects, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Frank Huebbers , Ali Dasdan , Yehea Ismail, Multi-layer interconnect performance corners for variation-aware timing analysis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California