Diagonal routing in high performance microprocessor design

ABSTRACT

This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan routing with horizontal and vertical directions, a new diagonal routing capability is added as one of the routing functions. With this enhancement, diagonal routing becomes an additional strategy for improving delays of critical paths in the microprocessor design. This method was applied to the prototype chip of the Fujitsu SPARC64 microprocessor with two CPU cores using 90nm process technology. By applying the diagonal routing to long distance nets, net length is reduced by 36% per net on average. When the diagonal routing is applied to a critical path, path delay is improved by as much as about 14 pico-seconds per net on a path. This improvement is more than the delay of a gate with no load. This prototype chip proved that our method was effective in reducing the total net length and improving path delays.

REFERENCES

• 1: Noriyuki Ito , Hiroaki Komatsu , Yoshiyasu Tanamura , Ryoichi Yamashita , Hiroyuki Sugiyama , Yaroku Sugiyama , Hirofumi Hamamura, A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor, Proceedings of the 21st International Conference on Computer Design, p.204, October 13-15, 2003
• 2: M. Nishihara, T. Murase, et al, "Single-Board CPU Packaging for the FACOM M-780", Fujitsu Scientific and Technical Journal, 23, 4, pp.226--235, 1987.
• 3: M. Oda, T. Hamaguchi, "Oblique Routing System for FACOM M-780 SSC", Fujitsu Scientific and Technical Journal, 23, 4, pp.236--242, 1987.
• 4: H. H. Chen, Routing L-shaped channels in nonslicing-structure placement, Proceedings of the 24th ACM/IEEE conference on Design automation, p.152-158, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37911]
• 5: David Marple , Michiel Smulders , Henk Hegen, An efficient compactor for 45° layout, Proceedings of the 25th ACM/IEEE conference on Design automation, p.396-402, June 12-15, 1988, Atlantic City, New Jersey, United States
• 6: C. Chiang, M. Sarrafzadeh, "Wirability of Knock-Knee Layouts with 45-degree wires", IEEE trans. On Circuits & Systems, vol. 38, No. 6, June 1991, pp. 613--624.
• 7: D. T. Lee, C. F. Shen, et at, "On Steiner Tree Problem with 45° Routing", Proc. ISCAS, pp. 1680--1682a, 1995.
• 8: S. Das , B. Bhattacharya, Channel routing in Manhattan-diagonal model, Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, p.43, January 03-06, 1996
• 9: Cheng-Kok Koh , Patrick H. Madden, Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures, Proceedings of the 10th Great Lakes symposium on VLSI, p.47-52, March 02-04, 2000, Chicago, Illinois, United States [doi>10.1145/330855.330961]
• 10: I. Mutsunori, T. Mitsuhashi, et al, "A Diagonal-Interconnect Architecture and Its Application to RISC Core Deisgn", Proc. ISSCC, pp. 684--689, 2002.
• 11: Hongyu Chen , Bo Yao , Feng Zhou , Chung-Kuan Cheng, The Y-architecture: yet another on-chip interconnect solution, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119957]
• 12: Ameya R. Agnihotri , Patrick H. Madden, Congestion reduction in traditional and new routing architectures, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA [doi>10.1145/764808.764862]
• 13: Charles Chiang , Qing Su , Ching-Shoei Chiang, Wirelength reduction by using diagonal wire, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA [doi>10.1145/764808.764836]
• 14: Takumi Maruyama, "SPARC64 VI: Fujitsu's Next Generation Processor", presented at the microprocessor forum, 2003..

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout

General Terms:
Design, Performance

Keywords:
diagonal routing, manhattan routing, microprocessor