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ABSTRACT

In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT_lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT_lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT_lottery outperforms several commonly-used arbitration algorithms today.

REFERENCES

• 1: C. H. Pyoun, C. H. Lin, H. S. Kim, and J. W. Chong, "The Efficient Bus Arbitration Scheme In Soc Environment," International Workshop on System-on-Chip for Real-Time Applications, 2003, Page(s):311 -- 315.
• 2: M. Yang, S. Q. Zheng, Bhagyavati, and S. Kurkovsky, "Programmable Weighted Arbiters for Constructing Switch Schedulers," Workshop on High Performance Switching and Routing, 2004, Page(s):203 -- 206.
• 3: Massimo Conti , Marco Caldari , Giovanni B. Vece , Simone Orcioni , Claudio Turchetti, Performance analysis of different arbitration algorithms of the AMBA AHB bus, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996734]
• 4: F. Poletti, D. Bertozzi, L. Benini, and A. Bogliolo, "Performance Analysis of Arbitration Policies for SoC Communication Architectures," Journal of Design Automation for Embedded Systems, 2003, Page(s):618 -- 621.
• 5: Kanishka Lahiri , Anand Raghunathan , Ganesh Lakshminarayana, LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs, Proceedings of the 38th conference on Design automation, p.15-20, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378252]
• 6: A. C. Waldspurger and W. E. Weih., "Lottery Scheduling: Flexible Proportional Share Resource Management," Symp. on Operating Systems Design and Implementation, 1994.
• 7: Kanishka Lahiri , Sujit Dey , Anand Raghunathan, Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.29, January 03-07, 2001

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Input/output circuits
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance