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ABSTRACT

This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis. Our multi-processor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os. However, this makes for a high level of power supply noise. We then applied an interface timing margin analysis tool that took power supply noise into account, and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board. As a result, we succeeded in operating the processor at 533MHz with the 2ch 64bit main memory IF at 266MHz and 64bit system bus at 178MHz.

REFERENCES

• 1: M. Matsumura et al., "Analysis of the Effects of Simultaneous Switching Noise on System Interface Timing Between LSIs," Collected papers of the 18th workshop on circuits and systems in Karuizawa, pp.43--48, 2005.
• 2: K. Kawasaki et al., "Single-Chip Multi-Processor integrating Quadruple Processors on 90nm CMOS Process," IEICE Technical Report, Vol. 105, No.95, pp.7--12, May.2005.
• 3: T. Sato et al., "LSI Noise Model for Power Integrity Analysis," FUJITSU, Vol.55, No.6, pp.608--613, Nov 2004
• 4: Atsuhiro Suga , Kunihiko Matsunami, Introducing the FR500 Embedded Microprocessor, IEEE Micro, v.20 n.4, p.21-27, July 2000 [doi>10.1109/40.865863]
• 5: H. Okano et al., "An 8-way VLIW Embedded Multimedia Processor Build in 7-layer Metal 0.11 μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 374--375, Feb. 2002.
• 6: Shiota et al., "A 51.2GOPS, 1.0GB/s-DMA Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors," ISSCC Dig. Tech. Papers, pp. 18--19, 2005.
• 7: Irvin M et al., "A new generation of MPEG-2 video encoder ASIC and its application to new technology markets," Broadcasting Convention, International (Conf. Publ. No. 428)12--16 Sept. 1996 Page(s):391--396.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures
          Subjects: RISC/CISC, VLIW architectures

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance