Hardware debugging method based on signal transitions and transactions

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Hardware debugging method based on signal transitions and transactions

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: Advances in simulation technologies table of contents

Pages: 454 - 459

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Nobuyuki Ohba	IBM Japan Ltd., Yamato city, Kanagawa, Japan
Kohji Takano	IBM Japan Ltd., Yamato city, Kanagawa, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 1

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ABSTRACT

This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. It can be programmed to generate a trigger for a logic analyzer when it detects certain transitions. The visualizer, which shows the captured data in the matrix, timing-chart, and state-transition diagram formats, helps the engineer effectively find bugs.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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