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Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Leading edge design methodology for SoCs and SiPs table of contents
Pages: 396 - 401  
Year of Publication: 2006
ISBN:0-7803-9451-8
Authors
Jesús Tabero  Instituto Nacional de Técnica Aeroespacial, Madrid, Spain
Julio Septién  Universidad Complutense de Madrid, Madrid, Spain
Hortensia Mecha  Universidad Complutense de Madrid, Madrid, Spain
Daniel Mozos  Universidad Complutense de Madrid, Madrid, Spain
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 38,   Citation Count: 1
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ABSTRACT

To get efficient HW management in 2D Reconfigurable Systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the task next to the borders of the free area for as many cycles as possible, trying to minimize the area fragmentation. Moreover, we combine it with a look-ahead heuristic that allows delaying the scheduling of a task to the next event, increasing the solution search space.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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O. F. Diessel, G. Wigley, "Opportunities for Operating Systems Research in Reconfigurable Computing", Technical Report ACRC-99-018. Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, 1999.
 
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O. F. Diessel, H. Elgindy, "On dynamic task scheduling for FPGA-based systems", International Journal of Foundations of Computer Science, IJFCS'01, Vol. 12, No. 5, 2001.
 
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A. Ahmadinia, C. Bobda, M. Bednara, J. Teich, "A new approach for on-line placement on reconfigurable devices", IPDPS-2004 (RAW'04), vol. 04, no. 4, p. 134a, 2004.
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J. Tabero J. Septién, H. Mecha, D. Mozos, "A vertex-list approach to 2D HW multitasking management in RTR FPGAs", DCIS 2003, Ciudad Real, Spain, pp. 545--550, Nov 2003.
 
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J. Tabero J. Septién, H. Mecha, D. Mozos, "A low fragmentation heuristic for task placement in 2D RTR HW management", FPL 2004, Antwerp, Belgium, pp. 241--250, Sep 2004


Collaborative Colleagues:
Jesús Tabero: colleagues
Julio Septién: colleagues
Hortensia Mecha: colleagues
Daniel Mozos: colleagues