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FastPlace 2.0: an efficient analytical placer for mixed-mode designs
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Placement table of contents
Pages: 195 - 200  
Year of Publication: 2006
ISBN:0-7803-9451-8
Authors
Natarajan Viswanathan  Iowa State University, Ames, IA
Min Pan  Iowa State University, Ames, IA
Chris Chu  Iowa State University, Ames, IA
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 27,   Citation Count: 2
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ABSTRACT

In this paper, we present FastPlace 2.0 - an extension to the efficient analytical standard-cell placer - FastPlace [15], to address the mixed-mode placement problem. The main contributions of our work are: (1) Extensions to the global placement framework of FastPlace to handle mixed-mode designs. (2) An efficient and optimal minimum perturbation macro legalization algorithm that is applied after global placement to resolve overlaps among the macros. (3) An efficient legalization scheme to legalize the standard cells among the placeable segments created after fixing the movable macros. On the ISPD 02 Mixed-Size placement benchmarks [31, our algorithm is 16.8X and 7.8X faster than state-of-the-art academic placers Capo 9.1 and Fengshui 5.0 respectively. Correspondingly, we are on average, 12% and 3% better in terms of wirelength over the respective placers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Standard performance evaluation corporation. http://www.spec.org/.
 
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S. N. Adya and I. L. Markov. ISPD02 IBM-MS Mixed-size Placement Benchmarks. http://vlsicad.eecs.umich.edu/BK/ISPD02bench/.
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S. Goto. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. Circuits and Systems, CAS-28(1):12--18, 1981.
 
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. VLSI module placement based on rectangle-packing by the sequence pair. IEEE Trans. Computer-Aided Design, 15(12):1518--1524, December 1996.
 
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M. Pan, N. Viswanathan, and C. Chu. An efficient and effective detailed placement algorithm. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 48--55, 2005.
 
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N. Viswanathan and C. C.-N. Chu. ISPD04 IBM Standard Cell Benchmarks with Pads. http://www.public.iastate.edu/~nataraj/ISPD04_Bench.html.
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Collaborative Colleagues:
Natarajan Viswanathan: colleagues
Min Pan: colleagues
Chris Chu: colleagues