Designing a custom architecture for DCT using NISC technology

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Designing a custom architecture for DCT using NISC technology

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: University design contest table of contents

Pages: 116 - 117

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Bita Gorjiara	University of California Irvine
Mehrdad Reshadi	University of California Irvine
Daniel Gajski	University of California Irvine

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 1

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ABSTRACT

This paper presents design of a custom architecture for Discrete Cosine Transform (DCT) using No-Instruction-Set Computer (NISC) technology that is developed for fast processor customization. Using several software transformations and hardware customization, we achieved up to 10 times performance improvement, 2 times power reduction, 12.8 times energy reduction, and 3 times area reduction compared to an already-optimized soft-core MIPS implementation.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	N. Ahmed, T. Natarajan, and K. R. Rao, Discrete Cosine Transform, IEEE Trans. On Computers, vol. C-23, pp. 90--93, Jan 1974
	2	Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar, ASIP Design Methodologies: Survey and Issues, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.76, January 03-07, 2001
	3	M. Reshadi, D. Gajski, A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths, In Proc. ISSS05, 2005.
	4	Mehrdad Reshadi , Bita Gorjiara , Daniel Gajski, Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths, Proceedings of the 2005 International Conference on Computer Design, p.69-76, October 02-05, 2005 [doi>10.1109/ICCD.2005.112]
	5	MIPS32® M4K#8482; Core, http://www.mips.com
	6	Design files: http://www.ece.uci.edu/~bgorjiar/projects/NISC/customDCT/
	7	Nisc webpage: http://www.ics.uci.edu/~reshadi/projects/nisc/