A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

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A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2006 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: University design contest table of contents

Pages: 108 - 109

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Minoru Watanabe	Kyushu Institute of Technology, Kawazu, Iizuka, Fukuoka, Japan
Fuminori Kobayashi	Kyushu Institute of Technology, Kawazu, Iizuka, Fukuoka, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 0

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ABSTRACT

High-speed reconfigurable processors have been developed in recent years: they are DAP/DNA chips and DRP chips [1][2]. These devices can be changed from one context to another context at every clock cycle in a few nanoseconds. However, their die size limits the number of reconfiguration contexts of currently available DAP/DNA and DRP chips to 4-16.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Nakano, T. Shindo, T. Kazami, M. Motomura, "Development of dynamically reconfigurable processor LSI," NEC Tech. J. (Japan), vol. 56, no. 4, pp. 99--102, 2003.
	2	http://www.ipflex.co.jp
	3	J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. R. Fossum, "Optically Programmable Gate Array," Proc. SPIE - Int. Soc. Opt. Eng., vol. 4089, pp. 763--771, 2000.
	4	J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, "Optical memory for computing and information processing," Proc. SPIE - Int. Soc. Opt. Eng., vol. 3804, pp. 14--24, 1999.
	5	M. Watanabe, F. Kobayashi, "A high-density optically reconfigurable gate array using dynamic method," International conference on Field-Programmable Logic and its Applications, pp. 261--269, 2004.
	6	M. Watanabe, F. Kobayashi, "A dynamic optically reconfigurable gate array using dynamic method," International Workshop on Applied Reconfigurable Computing, pp. 50--58, 2005.