The scaling of interconnect buffer needs

ABSTRACT

Since wires scale worse than devices, their quadratic delay is often linearized through buffer insertion, leading to a rapid increase in the number of buffers in a design when it is shrunk to successive process nodes. This increase was quantified in an influential work in 2003 by scaling the wiring distribution of a design block and measuring the number of buffers required by it at different process nodes. In this paper, we study the robustness of the data points presented in that work by examining their underlying assumptions. Finally, we revisit the CAD and design implications of buffer count growth, in light of current design trends.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Experimentation, Measurement, Performance, Theory

Keywords:
buffers, interconnect, repeaters, scaling